1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright © 2019 Intel Corporation
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef __INTEL_DE_H__
7*4882a593Smuzhiyun #define __INTEL_DE_H__
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include "i915_drv.h"
10*4882a593Smuzhiyun #include "i915_reg.h"
11*4882a593Smuzhiyun #include "intel_uncore.h"
12*4882a593Smuzhiyun
13*4882a593Smuzhiyun static inline u32
intel_de_read(struct drm_i915_private * i915,i915_reg_t reg)14*4882a593Smuzhiyun intel_de_read(struct drm_i915_private *i915, i915_reg_t reg)
15*4882a593Smuzhiyun {
16*4882a593Smuzhiyun return intel_uncore_read(&i915->uncore, reg);
17*4882a593Smuzhiyun }
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun static inline void
intel_de_posting_read(struct drm_i915_private * i915,i915_reg_t reg)20*4882a593Smuzhiyun intel_de_posting_read(struct drm_i915_private *i915, i915_reg_t reg)
21*4882a593Smuzhiyun {
22*4882a593Smuzhiyun intel_uncore_posting_read(&i915->uncore, reg);
23*4882a593Smuzhiyun }
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Note: read the warnings for intel_uncore_*_fw() functions! */
26*4882a593Smuzhiyun static inline u32
intel_de_read_fw(struct drm_i915_private * i915,i915_reg_t reg)27*4882a593Smuzhiyun intel_de_read_fw(struct drm_i915_private *i915, i915_reg_t reg)
28*4882a593Smuzhiyun {
29*4882a593Smuzhiyun return intel_uncore_read_fw(&i915->uncore, reg);
30*4882a593Smuzhiyun }
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun static inline void
intel_de_write(struct drm_i915_private * i915,i915_reg_t reg,u32 val)33*4882a593Smuzhiyun intel_de_write(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
34*4882a593Smuzhiyun {
35*4882a593Smuzhiyun intel_uncore_write(&i915->uncore, reg, val);
36*4882a593Smuzhiyun }
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* Note: read the warnings for intel_uncore_*_fw() functions! */
39*4882a593Smuzhiyun static inline void
intel_de_write_fw(struct drm_i915_private * i915,i915_reg_t reg,u32 val)40*4882a593Smuzhiyun intel_de_write_fw(struct drm_i915_private *i915, i915_reg_t reg, u32 val)
41*4882a593Smuzhiyun {
42*4882a593Smuzhiyun intel_uncore_write_fw(&i915->uncore, reg, val);
43*4882a593Smuzhiyun }
44*4882a593Smuzhiyun
45*4882a593Smuzhiyun static inline void
intel_de_rmw(struct drm_i915_private * i915,i915_reg_t reg,u32 clear,u32 set)46*4882a593Smuzhiyun intel_de_rmw(struct drm_i915_private *i915, i915_reg_t reg, u32 clear, u32 set)
47*4882a593Smuzhiyun {
48*4882a593Smuzhiyun intel_uncore_rmw(&i915->uncore, reg, clear, set);
49*4882a593Smuzhiyun }
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun static inline int
intel_de_wait_for_register(struct drm_i915_private * i915,i915_reg_t reg,u32 mask,u32 value,unsigned int timeout)52*4882a593Smuzhiyun intel_de_wait_for_register(struct drm_i915_private *i915, i915_reg_t reg,
53*4882a593Smuzhiyun u32 mask, u32 value, unsigned int timeout)
54*4882a593Smuzhiyun {
55*4882a593Smuzhiyun return intel_wait_for_register(&i915->uncore, reg, mask, value, timeout);
56*4882a593Smuzhiyun }
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun static inline int
intel_de_wait_for_set(struct drm_i915_private * i915,i915_reg_t reg,u32 mask,unsigned int timeout)59*4882a593Smuzhiyun intel_de_wait_for_set(struct drm_i915_private *i915, i915_reg_t reg,
60*4882a593Smuzhiyun u32 mask, unsigned int timeout)
61*4882a593Smuzhiyun {
62*4882a593Smuzhiyun return intel_de_wait_for_register(i915, reg, mask, mask, timeout);
63*4882a593Smuzhiyun }
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun static inline int
intel_de_wait_for_clear(struct drm_i915_private * i915,i915_reg_t reg,u32 mask,unsigned int timeout)66*4882a593Smuzhiyun intel_de_wait_for_clear(struct drm_i915_private *i915, i915_reg_t reg,
67*4882a593Smuzhiyun u32 mask, unsigned int timeout)
68*4882a593Smuzhiyun {
69*4882a593Smuzhiyun return intel_de_wait_for_register(i915, reg, mask, 0, timeout);
70*4882a593Smuzhiyun }
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun #endif /* __INTEL_DE_H__ */
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