1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright © 2019 Intel Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __INTEL_DDI_H__ 7*4882a593Smuzhiyun #define __INTEL_DDI_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include "intel_display.h" 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct drm_connector_state; 12*4882a593Smuzhiyun struct drm_i915_private; 13*4882a593Smuzhiyun struct intel_connector; 14*4882a593Smuzhiyun struct intel_crtc; 15*4882a593Smuzhiyun struct intel_crtc_state; 16*4882a593Smuzhiyun struct intel_dp; 17*4882a593Smuzhiyun struct intel_dpll_hw_state; 18*4882a593Smuzhiyun struct intel_encoder; 19*4882a593Smuzhiyun enum transcoder; 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun void intel_ddi_fdi_post_disable(struct intel_atomic_state *state, 22*4882a593Smuzhiyun struct intel_encoder *intel_encoder, 23*4882a593Smuzhiyun const struct intel_crtc_state *old_crtc_state, 24*4882a593Smuzhiyun const struct drm_connector_state *old_conn_state); 25*4882a593Smuzhiyun void hsw_fdi_link_train(struct intel_encoder *encoder, 26*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state); 27*4882a593Smuzhiyun void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port); 28*4882a593Smuzhiyun bool intel_ddi_get_hw_state(struct intel_encoder *encoder, enum pipe *pipe); 29*4882a593Smuzhiyun void intel_ddi_enable_transcoder_func(struct intel_encoder *encoder, 30*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state); 31*4882a593Smuzhiyun void intel_ddi_disable_transcoder_func(const struct intel_crtc_state *crtc_state); 32*4882a593Smuzhiyun void intel_ddi_enable_pipe_clock(struct intel_encoder *encoder, 33*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state); 34*4882a593Smuzhiyun void intel_ddi_disable_pipe_clock(const struct intel_crtc_state *crtc_state); 35*4882a593Smuzhiyun void intel_ddi_set_dp_msa(const struct intel_crtc_state *crtc_state, 36*4882a593Smuzhiyun const struct drm_connector_state *conn_state); 37*4882a593Smuzhiyun bool intel_ddi_connector_get_hw_state(struct intel_connector *intel_connector); 38*4882a593Smuzhiyun void intel_ddi_get_config(struct intel_encoder *encoder, 39*4882a593Smuzhiyun struct intel_crtc_state *pipe_config); 40*4882a593Smuzhiyun void intel_ddi_set_vc_payload_alloc(const struct intel_crtc_state *crtc_state, 41*4882a593Smuzhiyun bool state); 42*4882a593Smuzhiyun void intel_ddi_compute_min_voltage_level(struct drm_i915_private *dev_priv, 43*4882a593Smuzhiyun struct intel_crtc_state *crtc_state); 44*4882a593Smuzhiyun u32 bxt_signal_levels(struct intel_dp *intel_dp); 45*4882a593Smuzhiyun u32 ddi_signal_levels(struct intel_dp *intel_dp); 46*4882a593Smuzhiyun int intel_ddi_toggle_hdcp_signalling(struct intel_encoder *intel_encoder, 47*4882a593Smuzhiyun enum transcoder cpu_transcoder, 48*4882a593Smuzhiyun bool enable); 49*4882a593Smuzhiyun void icl_sanitize_encoder_pll_mapping(struct intel_encoder *encoder); 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun #endif /* __INTEL_DDI_H__ */ 52