1*4882a593Smuzhiyun /* SPDX-License-Identifier: MIT */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright © 2019 Intel Corporation 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __INTEL_BW_H__ 7*4882a593Smuzhiyun #define __INTEL_BW_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun #include <drm/drm_atomic.h> 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #include "intel_display.h" 12*4882a593Smuzhiyun #include "intel_display_power.h" 13*4882a593Smuzhiyun #include "intel_global_state.h" 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun struct drm_i915_private; 16*4882a593Smuzhiyun struct intel_atomic_state; 17*4882a593Smuzhiyun struct intel_crtc_state; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct intel_dbuf_bw { 20*4882a593Smuzhiyun int used_bw[I915_MAX_DBUF_SLICES]; 21*4882a593Smuzhiyun }; 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun struct intel_bw_state { 24*4882a593Smuzhiyun struct intel_global_state base; 25*4882a593Smuzhiyun struct intel_dbuf_bw dbuf_bw[I915_MAX_PIPES]; 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* 28*4882a593Smuzhiyun * Contains a bit mask, used to determine, whether correspondent 29*4882a593Smuzhiyun * pipe allows SAGV or not. 30*4882a593Smuzhiyun */ 31*4882a593Smuzhiyun u8 pipe_sagv_reject; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * Current QGV points mask, which restricts 35*4882a593Smuzhiyun * some particular SAGV states, not to confuse 36*4882a593Smuzhiyun * with pipe_sagv_mask. 37*4882a593Smuzhiyun */ 38*4882a593Smuzhiyun u8 qgv_points_mask; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun unsigned int data_rate[I915_MAX_PIPES]; 41*4882a593Smuzhiyun u8 num_active_planes[I915_MAX_PIPES]; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* bitmask of active pipes */ 44*4882a593Smuzhiyun u8 active_pipes; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun int min_cdclk; 47*4882a593Smuzhiyun }; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define to_intel_bw_state(x) container_of((x), struct intel_bw_state, base) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct intel_bw_state * 52*4882a593Smuzhiyun intel_atomic_get_old_bw_state(struct intel_atomic_state *state); 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun struct intel_bw_state * 55*4882a593Smuzhiyun intel_atomic_get_new_bw_state(struct intel_atomic_state *state); 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct intel_bw_state * 58*4882a593Smuzhiyun intel_atomic_get_bw_state(struct intel_atomic_state *state); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun void intel_bw_init_hw(struct drm_i915_private *dev_priv); 61*4882a593Smuzhiyun int intel_bw_init(struct drm_i915_private *dev_priv); 62*4882a593Smuzhiyun int intel_bw_atomic_check(struct intel_atomic_state *state); 63*4882a593Smuzhiyun void intel_bw_crtc_update(struct intel_bw_state *bw_state, 64*4882a593Smuzhiyun const struct intel_crtc_state *crtc_state); 65*4882a593Smuzhiyun int icl_pcode_restrict_qgv_points(struct drm_i915_private *dev_priv, 66*4882a593Smuzhiyun u32 points_mask); 67*4882a593Smuzhiyun int intel_bw_calc_min_cdclk(struct intel_atomic_state *state); 68*4882a593Smuzhiyun int skl_bw_calc_min_cdclk(struct intel_atomic_state *state); 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun #endif /* __INTEL_BW_H__ */ 71