1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright © 2007 Dave Mueller
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next
12*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the
13*4882a593Smuzhiyun * Software.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21*4882a593Smuzhiyun * IN THE SOFTWARE.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * Authors:
24*4882a593Smuzhiyun * Dave Mueller <dave.mueller@gmx.ch>
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun */
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun #include "intel_display_types.h"
29*4882a593Smuzhiyun #include "intel_dvo_dev.h"
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun /* register definitions according to the TFP410 data sheet */
32*4882a593Smuzhiyun #define TFP410_VID 0x014C
33*4882a593Smuzhiyun #define TFP410_DID 0x0410
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define TFP410_VID_LO 0x00
36*4882a593Smuzhiyun #define TFP410_VID_HI 0x01
37*4882a593Smuzhiyun #define TFP410_DID_LO 0x02
38*4882a593Smuzhiyun #define TFP410_DID_HI 0x03
39*4882a593Smuzhiyun #define TFP410_REV 0x04
40*4882a593Smuzhiyun
41*4882a593Smuzhiyun #define TFP410_CTL_1 0x08
42*4882a593Smuzhiyun #define TFP410_CTL_1_TDIS (1<<6)
43*4882a593Smuzhiyun #define TFP410_CTL_1_VEN (1<<5)
44*4882a593Smuzhiyun #define TFP410_CTL_1_HEN (1<<4)
45*4882a593Smuzhiyun #define TFP410_CTL_1_DSEL (1<<3)
46*4882a593Smuzhiyun #define TFP410_CTL_1_BSEL (1<<2)
47*4882a593Smuzhiyun #define TFP410_CTL_1_EDGE (1<<1)
48*4882a593Smuzhiyun #define TFP410_CTL_1_PD (1<<0)
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun #define TFP410_CTL_2 0x09
51*4882a593Smuzhiyun #define TFP410_CTL_2_VLOW (1<<7)
52*4882a593Smuzhiyun #define TFP410_CTL_2_MSEL_MASK (0x7<<4)
53*4882a593Smuzhiyun #define TFP410_CTL_2_MSEL (1<<4)
54*4882a593Smuzhiyun #define TFP410_CTL_2_TSEL (1<<3)
55*4882a593Smuzhiyun #define TFP410_CTL_2_RSEN (1<<2)
56*4882a593Smuzhiyun #define TFP410_CTL_2_HTPLG (1<<1)
57*4882a593Smuzhiyun #define TFP410_CTL_2_MDI (1<<0)
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun #define TFP410_CTL_3 0x0A
60*4882a593Smuzhiyun #define TFP410_CTL_3_DK_MASK (0x7<<5)
61*4882a593Smuzhiyun #define TFP410_CTL_3_DK (1<<5)
62*4882a593Smuzhiyun #define TFP410_CTL_3_DKEN (1<<4)
63*4882a593Smuzhiyun #define TFP410_CTL_3_CTL_MASK (0x7<<1)
64*4882a593Smuzhiyun #define TFP410_CTL_3_CTL (1<<1)
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun #define TFP410_USERCFG 0x0B
67*4882a593Smuzhiyun
68*4882a593Smuzhiyun #define TFP410_DE_DLY 0x32
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun #define TFP410_DE_CTL 0x33
71*4882a593Smuzhiyun #define TFP410_DE_CTL_DEGEN (1<<6)
72*4882a593Smuzhiyun #define TFP410_DE_CTL_VSPOL (1<<5)
73*4882a593Smuzhiyun #define TFP410_DE_CTL_HSPOL (1<<4)
74*4882a593Smuzhiyun #define TFP410_DE_CTL_DEDLY8 (1<<0)
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun #define TFP410_DE_TOP 0x34
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun #define TFP410_DE_CNT_LO 0x36
79*4882a593Smuzhiyun #define TFP410_DE_CNT_HI 0x37
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun #define TFP410_DE_LIN_LO 0x38
82*4882a593Smuzhiyun #define TFP410_DE_LIN_HI 0x39
83*4882a593Smuzhiyun
84*4882a593Smuzhiyun #define TFP410_H_RES_LO 0x3A
85*4882a593Smuzhiyun #define TFP410_H_RES_HI 0x3B
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun #define TFP410_V_RES_LO 0x3C
88*4882a593Smuzhiyun #define TFP410_V_RES_HI 0x3D
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun struct tfp410_priv {
91*4882a593Smuzhiyun bool quiet;
92*4882a593Smuzhiyun };
93*4882a593Smuzhiyun
tfp410_readb(struct intel_dvo_device * dvo,int addr,u8 * ch)94*4882a593Smuzhiyun static bool tfp410_readb(struct intel_dvo_device *dvo, int addr, u8 *ch)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun struct tfp410_priv *tfp = dvo->dev_priv;
97*4882a593Smuzhiyun struct i2c_adapter *adapter = dvo->i2c_bus;
98*4882a593Smuzhiyun u8 out_buf[2];
99*4882a593Smuzhiyun u8 in_buf[2];
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun struct i2c_msg msgs[] = {
102*4882a593Smuzhiyun {
103*4882a593Smuzhiyun .addr = dvo->slave_addr,
104*4882a593Smuzhiyun .flags = 0,
105*4882a593Smuzhiyun .len = 1,
106*4882a593Smuzhiyun .buf = out_buf,
107*4882a593Smuzhiyun },
108*4882a593Smuzhiyun {
109*4882a593Smuzhiyun .addr = dvo->slave_addr,
110*4882a593Smuzhiyun .flags = I2C_M_RD,
111*4882a593Smuzhiyun .len = 1,
112*4882a593Smuzhiyun .buf = in_buf,
113*4882a593Smuzhiyun }
114*4882a593Smuzhiyun };
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun out_buf[0] = addr;
117*4882a593Smuzhiyun out_buf[1] = 0;
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun if (i2c_transfer(adapter, msgs, 2) == 2) {
120*4882a593Smuzhiyun *ch = in_buf[0];
121*4882a593Smuzhiyun return true;
122*4882a593Smuzhiyun }
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun if (!tfp->quiet) {
125*4882a593Smuzhiyun DRM_DEBUG_KMS("Unable to read register 0x%02x from %s:%02x.\n",
126*4882a593Smuzhiyun addr, adapter->name, dvo->slave_addr);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun return false;
129*4882a593Smuzhiyun }
130*4882a593Smuzhiyun
tfp410_writeb(struct intel_dvo_device * dvo,int addr,u8 ch)131*4882a593Smuzhiyun static bool tfp410_writeb(struct intel_dvo_device *dvo, int addr, u8 ch)
132*4882a593Smuzhiyun {
133*4882a593Smuzhiyun struct tfp410_priv *tfp = dvo->dev_priv;
134*4882a593Smuzhiyun struct i2c_adapter *adapter = dvo->i2c_bus;
135*4882a593Smuzhiyun u8 out_buf[2];
136*4882a593Smuzhiyun struct i2c_msg msg = {
137*4882a593Smuzhiyun .addr = dvo->slave_addr,
138*4882a593Smuzhiyun .flags = 0,
139*4882a593Smuzhiyun .len = 2,
140*4882a593Smuzhiyun .buf = out_buf,
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun
143*4882a593Smuzhiyun out_buf[0] = addr;
144*4882a593Smuzhiyun out_buf[1] = ch;
145*4882a593Smuzhiyun
146*4882a593Smuzhiyun if (i2c_transfer(adapter, &msg, 1) == 1)
147*4882a593Smuzhiyun return true;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun if (!tfp->quiet) {
150*4882a593Smuzhiyun DRM_DEBUG_KMS("Unable to write register 0x%02x to %s:%d.\n",
151*4882a593Smuzhiyun addr, adapter->name, dvo->slave_addr);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
154*4882a593Smuzhiyun return false;
155*4882a593Smuzhiyun }
156*4882a593Smuzhiyun
tfp410_getid(struct intel_dvo_device * dvo,int addr)157*4882a593Smuzhiyun static int tfp410_getid(struct intel_dvo_device *dvo, int addr)
158*4882a593Smuzhiyun {
159*4882a593Smuzhiyun u8 ch1, ch2;
160*4882a593Smuzhiyun
161*4882a593Smuzhiyun if (tfp410_readb(dvo, addr+0, &ch1) &&
162*4882a593Smuzhiyun tfp410_readb(dvo, addr+1, &ch2))
163*4882a593Smuzhiyun return ((ch2 << 8) & 0xFF00) | (ch1 & 0x00FF);
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun return -1;
166*4882a593Smuzhiyun }
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun /* Ti TFP410 driver for chip on i2c bus */
tfp410_init(struct intel_dvo_device * dvo,struct i2c_adapter * adapter)169*4882a593Smuzhiyun static bool tfp410_init(struct intel_dvo_device *dvo,
170*4882a593Smuzhiyun struct i2c_adapter *adapter)
171*4882a593Smuzhiyun {
172*4882a593Smuzhiyun /* this will detect the tfp410 chip on the specified i2c bus */
173*4882a593Smuzhiyun struct tfp410_priv *tfp;
174*4882a593Smuzhiyun int id;
175*4882a593Smuzhiyun
176*4882a593Smuzhiyun tfp = kzalloc(sizeof(struct tfp410_priv), GFP_KERNEL);
177*4882a593Smuzhiyun if (tfp == NULL)
178*4882a593Smuzhiyun return false;
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun dvo->i2c_bus = adapter;
181*4882a593Smuzhiyun dvo->dev_priv = tfp;
182*4882a593Smuzhiyun tfp->quiet = true;
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun if ((id = tfp410_getid(dvo, TFP410_VID_LO)) != TFP410_VID) {
185*4882a593Smuzhiyun DRM_DEBUG_KMS("tfp410 not detected got VID %X: from %s "
186*4882a593Smuzhiyun "Slave %d.\n",
187*4882a593Smuzhiyun id, adapter->name, dvo->slave_addr);
188*4882a593Smuzhiyun goto out;
189*4882a593Smuzhiyun }
190*4882a593Smuzhiyun
191*4882a593Smuzhiyun if ((id = tfp410_getid(dvo, TFP410_DID_LO)) != TFP410_DID) {
192*4882a593Smuzhiyun DRM_DEBUG_KMS("tfp410 not detected got DID %X: from %s "
193*4882a593Smuzhiyun "Slave %d.\n",
194*4882a593Smuzhiyun id, adapter->name, dvo->slave_addr);
195*4882a593Smuzhiyun goto out;
196*4882a593Smuzhiyun }
197*4882a593Smuzhiyun tfp->quiet = false;
198*4882a593Smuzhiyun return true;
199*4882a593Smuzhiyun out:
200*4882a593Smuzhiyun kfree(tfp);
201*4882a593Smuzhiyun return false;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
tfp410_detect(struct intel_dvo_device * dvo)204*4882a593Smuzhiyun static enum drm_connector_status tfp410_detect(struct intel_dvo_device *dvo)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun enum drm_connector_status ret = connector_status_disconnected;
207*4882a593Smuzhiyun u8 ctl2;
208*4882a593Smuzhiyun
209*4882a593Smuzhiyun if (tfp410_readb(dvo, TFP410_CTL_2, &ctl2)) {
210*4882a593Smuzhiyun if (ctl2 & TFP410_CTL_2_RSEN)
211*4882a593Smuzhiyun ret = connector_status_connected;
212*4882a593Smuzhiyun else
213*4882a593Smuzhiyun ret = connector_status_disconnected;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun return ret;
217*4882a593Smuzhiyun }
218*4882a593Smuzhiyun
tfp410_mode_valid(struct intel_dvo_device * dvo,struct drm_display_mode * mode)219*4882a593Smuzhiyun static enum drm_mode_status tfp410_mode_valid(struct intel_dvo_device *dvo,
220*4882a593Smuzhiyun struct drm_display_mode *mode)
221*4882a593Smuzhiyun {
222*4882a593Smuzhiyun return MODE_OK;
223*4882a593Smuzhiyun }
224*4882a593Smuzhiyun
tfp410_mode_set(struct intel_dvo_device * dvo,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)225*4882a593Smuzhiyun static void tfp410_mode_set(struct intel_dvo_device *dvo,
226*4882a593Smuzhiyun const struct drm_display_mode *mode,
227*4882a593Smuzhiyun const struct drm_display_mode *adjusted_mode)
228*4882a593Smuzhiyun {
229*4882a593Smuzhiyun /* As long as the basics are set up, since we don't have clock dependencies
230*4882a593Smuzhiyun * in the mode setup, we can just leave the registers alone and everything
231*4882a593Smuzhiyun * will work fine.
232*4882a593Smuzhiyun */
233*4882a593Smuzhiyun /* don't do much */
234*4882a593Smuzhiyun return;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun /* set the tfp410 power state */
tfp410_dpms(struct intel_dvo_device * dvo,bool enable)238*4882a593Smuzhiyun static void tfp410_dpms(struct intel_dvo_device *dvo, bool enable)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun u8 ctl1;
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1))
243*4882a593Smuzhiyun return;
244*4882a593Smuzhiyun
245*4882a593Smuzhiyun if (enable)
246*4882a593Smuzhiyun ctl1 |= TFP410_CTL_1_PD;
247*4882a593Smuzhiyun else
248*4882a593Smuzhiyun ctl1 &= ~TFP410_CTL_1_PD;
249*4882a593Smuzhiyun
250*4882a593Smuzhiyun tfp410_writeb(dvo, TFP410_CTL_1, ctl1);
251*4882a593Smuzhiyun }
252*4882a593Smuzhiyun
tfp410_get_hw_state(struct intel_dvo_device * dvo)253*4882a593Smuzhiyun static bool tfp410_get_hw_state(struct intel_dvo_device *dvo)
254*4882a593Smuzhiyun {
255*4882a593Smuzhiyun u8 ctl1;
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun if (!tfp410_readb(dvo, TFP410_CTL_1, &ctl1))
258*4882a593Smuzhiyun return false;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun if (ctl1 & TFP410_CTL_1_PD)
261*4882a593Smuzhiyun return true;
262*4882a593Smuzhiyun else
263*4882a593Smuzhiyun return false;
264*4882a593Smuzhiyun }
265*4882a593Smuzhiyun
tfp410_dump_regs(struct intel_dvo_device * dvo)266*4882a593Smuzhiyun static void tfp410_dump_regs(struct intel_dvo_device *dvo)
267*4882a593Smuzhiyun {
268*4882a593Smuzhiyun u8 val, val2;
269*4882a593Smuzhiyun
270*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_REV, &val);
271*4882a593Smuzhiyun DRM_DEBUG_KMS("TFP410_REV: 0x%02X\n", val);
272*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_CTL_1, &val);
273*4882a593Smuzhiyun DRM_DEBUG_KMS("TFP410_CTL1: 0x%02X\n", val);
274*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_CTL_2, &val);
275*4882a593Smuzhiyun DRM_DEBUG_KMS("TFP410_CTL2: 0x%02X\n", val);
276*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_CTL_3, &val);
277*4882a593Smuzhiyun DRM_DEBUG_KMS("TFP410_CTL3: 0x%02X\n", val);
278*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_USERCFG, &val);
279*4882a593Smuzhiyun DRM_DEBUG_KMS("TFP410_USERCFG: 0x%02X\n", val);
280*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_DE_DLY, &val);
281*4882a593Smuzhiyun DRM_DEBUG_KMS("TFP410_DE_DLY: 0x%02X\n", val);
282*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_DE_CTL, &val);
283*4882a593Smuzhiyun DRM_DEBUG_KMS("TFP410_DE_CTL: 0x%02X\n", val);
284*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_DE_TOP, &val);
285*4882a593Smuzhiyun DRM_DEBUG_KMS("TFP410_DE_TOP: 0x%02X\n", val);
286*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_DE_CNT_LO, &val);
287*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_DE_CNT_HI, &val2);
288*4882a593Smuzhiyun DRM_DEBUG_KMS("TFP410_DE_CNT: 0x%02X%02X\n", val2, val);
289*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_DE_LIN_LO, &val);
290*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_DE_LIN_HI, &val2);
291*4882a593Smuzhiyun DRM_DEBUG_KMS("TFP410_DE_LIN: 0x%02X%02X\n", val2, val);
292*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_H_RES_LO, &val);
293*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_H_RES_HI, &val2);
294*4882a593Smuzhiyun DRM_DEBUG_KMS("TFP410_H_RES: 0x%02X%02X\n", val2, val);
295*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_V_RES_LO, &val);
296*4882a593Smuzhiyun tfp410_readb(dvo, TFP410_V_RES_HI, &val2);
297*4882a593Smuzhiyun DRM_DEBUG_KMS("TFP410_V_RES: 0x%02X%02X\n", val2, val);
298*4882a593Smuzhiyun }
299*4882a593Smuzhiyun
tfp410_destroy(struct intel_dvo_device * dvo)300*4882a593Smuzhiyun static void tfp410_destroy(struct intel_dvo_device *dvo)
301*4882a593Smuzhiyun {
302*4882a593Smuzhiyun struct tfp410_priv *tfp = dvo->dev_priv;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun if (tfp) {
305*4882a593Smuzhiyun kfree(tfp);
306*4882a593Smuzhiyun dvo->dev_priv = NULL;
307*4882a593Smuzhiyun }
308*4882a593Smuzhiyun }
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun const struct intel_dvo_dev_ops tfp410_ops = {
311*4882a593Smuzhiyun .init = tfp410_init,
312*4882a593Smuzhiyun .detect = tfp410_detect,
313*4882a593Smuzhiyun .mode_valid = tfp410_mode_valid,
314*4882a593Smuzhiyun .mode_set = tfp410_mode_set,
315*4882a593Smuzhiyun .dpms = tfp410_dpms,
316*4882a593Smuzhiyun .get_hw_state = tfp410_get_hw_state,
317*4882a593Smuzhiyun .dump_regs = tfp410_dump_regs,
318*4882a593Smuzhiyun .destroy = tfp410_destroy,
319*4882a593Smuzhiyun };
320