1*4882a593Smuzhiyunconfig DRM_I915_FENCE_TIMEOUT 2*4882a593Smuzhiyun int "Timeout for unsignaled foreign fences (ms, jiffy granularity)" 3*4882a593Smuzhiyun default 10000 # milliseconds 4*4882a593Smuzhiyun help 5*4882a593Smuzhiyun When listening to a foreign fence, we install a supplementary timer 6*4882a593Smuzhiyun to ensure that we are always signaled and our userspace is able to 7*4882a593Smuzhiyun make forward progress. This value specifies the timeout used for an 8*4882a593Smuzhiyun unsignaled foreign fence. 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun May be 0 to disable the timeout, and rely on the foreign fence being 11*4882a593Smuzhiyun eventually signaled. 12*4882a593Smuzhiyun 13*4882a593Smuzhiyunconfig DRM_I915_USERFAULT_AUTOSUSPEND 14*4882a593Smuzhiyun int "Runtime autosuspend delay for userspace GGTT mmaps (ms)" 15*4882a593Smuzhiyun default 250 # milliseconds 16*4882a593Smuzhiyun help 17*4882a593Smuzhiyun On runtime suspend, as we suspend the device, we have to revoke 18*4882a593Smuzhiyun userspace GGTT mmaps and force userspace to take a pagefault on 19*4882a593Smuzhiyun their next access. The revocation and subsequent recreation of 20*4882a593Smuzhiyun the GGTT mmap can be very slow and so we impose a small hysteris 21*4882a593Smuzhiyun that complements the runtime-pm autosuspend and provides a lower 22*4882a593Smuzhiyun floor on the autosuspend delay. 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun May be 0 to disable the extra delay and solely use the device level 25*4882a593Smuzhiyun runtime pm autosuspend delay tunable. 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunconfig DRM_I915_HEARTBEAT_INTERVAL 28*4882a593Smuzhiyun int "Interval between heartbeat pulses (ms)" 29*4882a593Smuzhiyun default 2500 # milliseconds 30*4882a593Smuzhiyun help 31*4882a593Smuzhiyun The driver sends a periodic heartbeat down all active engines to 32*4882a593Smuzhiyun check the health of the GPU and undertake regular house-keeping of 33*4882a593Smuzhiyun internal driver state. 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun This is adjustable via 36*4882a593Smuzhiyun /sys/class/drm/card?/engine/*/heartbeat_interval_ms 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun May be 0 to disable heartbeats and therefore disable automatic GPU 39*4882a593Smuzhiyun hang detection. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunconfig DRM_I915_PREEMPT_TIMEOUT 42*4882a593Smuzhiyun int "Preempt timeout (ms, jiffy granularity)" 43*4882a593Smuzhiyun default 640 # milliseconds 44*4882a593Smuzhiyun help 45*4882a593Smuzhiyun How long to wait (in milliseconds) for a preemption event to occur 46*4882a593Smuzhiyun when submitting a new context via execlists. If the current context 47*4882a593Smuzhiyun does not hit an arbitration point and yield to HW before the timer 48*4882a593Smuzhiyun expires, the HW will be reset to allow the more important context 49*4882a593Smuzhiyun to execute. 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun This is adjustable via 52*4882a593Smuzhiyun /sys/class/drm/card?/engine/*/preempt_timeout_ms 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun May be 0 to disable the timeout. 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun The compiled in default may get overridden at driver probe time on 57*4882a593Smuzhiyun certain platforms and certain engines which will be reflected in the 58*4882a593Smuzhiyun sysfs control. 59*4882a593Smuzhiyun 60*4882a593Smuzhiyunconfig DRM_I915_MAX_REQUEST_BUSYWAIT 61*4882a593Smuzhiyun int "Busywait for request completion limit (ns)" 62*4882a593Smuzhiyun default 8000 # nanoseconds 63*4882a593Smuzhiyun help 64*4882a593Smuzhiyun Before sleeping waiting for a request (GPU operation) to complete, 65*4882a593Smuzhiyun we may spend some time polling for its completion. As the IRQ may 66*4882a593Smuzhiyun take a non-negligible time to setup, we do a short spin first to 67*4882a593Smuzhiyun check if the request will complete in the time it would have taken 68*4882a593Smuzhiyun us to enable the interrupt. 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun This is adjustable via 71*4882a593Smuzhiyun /sys/class/drm/card?/engine/*/max_busywait_duration_ns 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun May be 0 to disable the initial spin. In practice, we estimate 74*4882a593Smuzhiyun the cost of enabling the interrupt (if currently disabled) to be 75*4882a593Smuzhiyun a few microseconds. 76*4882a593Smuzhiyun 77*4882a593Smuzhiyunconfig DRM_I915_STOP_TIMEOUT 78*4882a593Smuzhiyun int "How long to wait for an engine to quiesce gracefully before reset (ms)" 79*4882a593Smuzhiyun default 100 # milliseconds 80*4882a593Smuzhiyun help 81*4882a593Smuzhiyun By stopping submission and sleeping for a short time before resetting 82*4882a593Smuzhiyun the GPU, we allow the innocent contexts also on the system to quiesce. 83*4882a593Smuzhiyun It is then less likely for a hanging context to cause collateral 84*4882a593Smuzhiyun damage as the system is reset in order to recover. The corollary is 85*4882a593Smuzhiyun that the reset itself may take longer and so be more disruptive to 86*4882a593Smuzhiyun interactive or low latency workloads. 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun This is adjustable via 89*4882a593Smuzhiyun /sys/class/drm/card?/engine/*/stop_timeout_ms 90*4882a593Smuzhiyun 91*4882a593Smuzhiyunconfig DRM_I915_TIMESLICE_DURATION 92*4882a593Smuzhiyun int "Scheduling quantum for userspace batches (ms, jiffy granularity)" 93*4882a593Smuzhiyun default 1 # milliseconds 94*4882a593Smuzhiyun help 95*4882a593Smuzhiyun When two user batches of equal priority are executing, we will 96*4882a593Smuzhiyun alternate execution of each batch to ensure forward progress of 97*4882a593Smuzhiyun all users. This is necessary in some cases where there may be 98*4882a593Smuzhiyun an implicit dependency between those batches that requires 99*4882a593Smuzhiyun concurrent execution in order for them to proceed, e.g. they 100*4882a593Smuzhiyun interact with each other via userspace semaphores. Each context 101*4882a593Smuzhiyun is scheduled for execution for the timeslice duration, before 102*4882a593Smuzhiyun switching to the next context. 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun This is adjustable via 105*4882a593Smuzhiyun /sys/class/drm/card?/engine/*/timeslice_duration_ms 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun May be 0 to disable timeslicing. 108