1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (c) 2009-2011, Intel Corporation.
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #ifndef __INTEL_DRV_H__
7*4882a593Smuzhiyun #define __INTEL_DRV_H__
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <linux/i2c.h>
10*4882a593Smuzhiyun #include <linux/i2c-algo-bit.h>
11*4882a593Smuzhiyun #include <drm/drm_crtc.h>
12*4882a593Smuzhiyun #include <drm/drm_crtc_helper.h>
13*4882a593Smuzhiyun #include <drm/drm_encoder.h>
14*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
15*4882a593Smuzhiyun #include <drm/drm_vblank.h>
16*4882a593Smuzhiyun #include "gma_display.h"
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /*
19*4882a593Smuzhiyun * Display related stuff
20*4882a593Smuzhiyun */
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun /* maximum connectors per crtcs in the mode set */
23*4882a593Smuzhiyun #define INTELFB_CONN_LIMIT 4
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* Intel Pipe Clone Bit */
26*4882a593Smuzhiyun #define INTEL_HDMIB_CLONE_BIT 1
27*4882a593Smuzhiyun #define INTEL_HDMIC_CLONE_BIT 2
28*4882a593Smuzhiyun #define INTEL_HDMID_CLONE_BIT 3
29*4882a593Smuzhiyun #define INTEL_HDMIE_CLONE_BIT 4
30*4882a593Smuzhiyun #define INTEL_HDMIF_CLONE_BIT 5
31*4882a593Smuzhiyun #define INTEL_SDVO_NON_TV_CLONE_BIT 6
32*4882a593Smuzhiyun #define INTEL_SDVO_TV_CLONE_BIT 7
33*4882a593Smuzhiyun #define INTEL_SDVO_LVDS_CLONE_BIT 8
34*4882a593Smuzhiyun #define INTEL_ANALOG_CLONE_BIT 9
35*4882a593Smuzhiyun #define INTEL_TV_CLONE_BIT 10
36*4882a593Smuzhiyun #define INTEL_DP_B_CLONE_BIT 11
37*4882a593Smuzhiyun #define INTEL_DP_C_CLONE_BIT 12
38*4882a593Smuzhiyun #define INTEL_DP_D_CLONE_BIT 13
39*4882a593Smuzhiyun #define INTEL_LVDS_CLONE_BIT 14
40*4882a593Smuzhiyun #define INTEL_DVO_TMDS_CLONE_BIT 15
41*4882a593Smuzhiyun #define INTEL_DVO_LVDS_CLONE_BIT 16
42*4882a593Smuzhiyun #define INTEL_EDP_CLONE_BIT 17
43*4882a593Smuzhiyun
44*4882a593Smuzhiyun /* these are outputs from the chip - integrated only
45*4882a593Smuzhiyun * external chips are via DVO or SDVO output */
46*4882a593Smuzhiyun #define INTEL_OUTPUT_UNUSED 0
47*4882a593Smuzhiyun #define INTEL_OUTPUT_ANALOG 1
48*4882a593Smuzhiyun #define INTEL_OUTPUT_DVO 2
49*4882a593Smuzhiyun #define INTEL_OUTPUT_SDVO 3
50*4882a593Smuzhiyun #define INTEL_OUTPUT_LVDS 4
51*4882a593Smuzhiyun #define INTEL_OUTPUT_TVOUT 5
52*4882a593Smuzhiyun #define INTEL_OUTPUT_HDMI 6
53*4882a593Smuzhiyun #define INTEL_OUTPUT_MIPI 7
54*4882a593Smuzhiyun #define INTEL_OUTPUT_MIPI2 8
55*4882a593Smuzhiyun #define INTEL_OUTPUT_DISPLAYPORT 9
56*4882a593Smuzhiyun #define INTEL_OUTPUT_EDP 10
57*4882a593Smuzhiyun
58*4882a593Smuzhiyun /*
59*4882a593Smuzhiyun * Hold information useally put on the device driver privates here,
60*4882a593Smuzhiyun * since it needs to be shared across multiple of devices drivers privates.
61*4882a593Smuzhiyun */
62*4882a593Smuzhiyun struct psb_intel_mode_device {
63*4882a593Smuzhiyun
64*4882a593Smuzhiyun /*
65*4882a593Smuzhiyun * Abstracted memory manager operations
66*4882a593Smuzhiyun */
67*4882a593Smuzhiyun size_t(*bo_offset) (struct drm_device *dev, void *bo);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun /*
70*4882a593Smuzhiyun * LVDS info
71*4882a593Smuzhiyun */
72*4882a593Smuzhiyun int backlight_duty_cycle; /* restore backlight to this value */
73*4882a593Smuzhiyun bool panel_wants_dither;
74*4882a593Smuzhiyun struct drm_display_mode *panel_fixed_mode;
75*4882a593Smuzhiyun struct drm_display_mode *panel_fixed_mode2;
76*4882a593Smuzhiyun struct drm_display_mode *vbt_mode; /* if any */
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun uint32_t saveBLC_PWM_CTL;
79*4882a593Smuzhiyun };
80*4882a593Smuzhiyun
81*4882a593Smuzhiyun struct psb_intel_i2c_chan {
82*4882a593Smuzhiyun /* for getting at dev. private (mmio etc.) */
83*4882a593Smuzhiyun struct drm_device *drm_dev;
84*4882a593Smuzhiyun u32 reg; /* GPIO reg */
85*4882a593Smuzhiyun struct i2c_adapter adapter;
86*4882a593Smuzhiyun struct i2c_algo_bit_data algo;
87*4882a593Smuzhiyun u8 slave_addr;
88*4882a593Smuzhiyun };
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun struct gma_encoder {
91*4882a593Smuzhiyun struct drm_encoder base;
92*4882a593Smuzhiyun int type;
93*4882a593Smuzhiyun bool needs_tv_clock;
94*4882a593Smuzhiyun void (*hot_plug)(struct gma_encoder *);
95*4882a593Smuzhiyun int crtc_mask;
96*4882a593Smuzhiyun int clone_mask;
97*4882a593Smuzhiyun u32 ddi_select; /* Channel info */
98*4882a593Smuzhiyun #define DDI0_SELECT 0x01
99*4882a593Smuzhiyun #define DDI1_SELECT 0x02
100*4882a593Smuzhiyun #define DP_MASK 0x8000
101*4882a593Smuzhiyun #define DDI_MASK 0x03
102*4882a593Smuzhiyun void *dev_priv; /* For sdvo_priv, lvds_priv, etc... */
103*4882a593Smuzhiyun
104*4882a593Smuzhiyun /* FIXME: Either make SDVO and LVDS store it's i2c here or give CDV it's
105*4882a593Smuzhiyun own set of output privates */
106*4882a593Smuzhiyun struct psb_intel_i2c_chan *i2c_bus;
107*4882a593Smuzhiyun struct psb_intel_i2c_chan *ddc_bus;
108*4882a593Smuzhiyun };
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun struct gma_connector {
111*4882a593Smuzhiyun struct drm_connector base;
112*4882a593Smuzhiyun struct gma_encoder *encoder;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun void (*save)(struct drm_connector *connector);
115*4882a593Smuzhiyun void (*restore)(struct drm_connector *connector);
116*4882a593Smuzhiyun };
117*4882a593Smuzhiyun
118*4882a593Smuzhiyun struct psb_intel_crtc_state {
119*4882a593Smuzhiyun uint32_t saveDSPCNTR;
120*4882a593Smuzhiyun uint32_t savePIPECONF;
121*4882a593Smuzhiyun uint32_t savePIPESRC;
122*4882a593Smuzhiyun uint32_t saveDPLL;
123*4882a593Smuzhiyun uint32_t saveFP0;
124*4882a593Smuzhiyun uint32_t saveFP1;
125*4882a593Smuzhiyun uint32_t saveHTOTAL;
126*4882a593Smuzhiyun uint32_t saveHBLANK;
127*4882a593Smuzhiyun uint32_t saveHSYNC;
128*4882a593Smuzhiyun uint32_t saveVTOTAL;
129*4882a593Smuzhiyun uint32_t saveVBLANK;
130*4882a593Smuzhiyun uint32_t saveVSYNC;
131*4882a593Smuzhiyun uint32_t saveDSPSTRIDE;
132*4882a593Smuzhiyun uint32_t saveDSPSIZE;
133*4882a593Smuzhiyun uint32_t saveDSPPOS;
134*4882a593Smuzhiyun uint32_t saveDSPBASE;
135*4882a593Smuzhiyun uint32_t savePalette[256];
136*4882a593Smuzhiyun };
137*4882a593Smuzhiyun
138*4882a593Smuzhiyun struct gma_crtc {
139*4882a593Smuzhiyun struct drm_crtc base;
140*4882a593Smuzhiyun int pipe;
141*4882a593Smuzhiyun int plane;
142*4882a593Smuzhiyun uint32_t cursor_addr;
143*4882a593Smuzhiyun struct gtt_range *cursor_gt;
144*4882a593Smuzhiyun u8 lut_adj[256];
145*4882a593Smuzhiyun struct psb_intel_framebuffer *fbdev_fb;
146*4882a593Smuzhiyun /* a mode_set for fbdev users on this crtc */
147*4882a593Smuzhiyun struct drm_mode_set mode_set;
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /* GEM object that holds our cursor */
150*4882a593Smuzhiyun struct drm_gem_object *cursor_obj;
151*4882a593Smuzhiyun
152*4882a593Smuzhiyun struct drm_display_mode saved_mode;
153*4882a593Smuzhiyun struct drm_display_mode saved_adjusted_mode;
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun struct psb_intel_mode_device *mode_dev;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun /*crtc mode setting flags*/
158*4882a593Smuzhiyun u32 mode_flags;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun bool active;
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun /* Saved Crtc HW states */
163*4882a593Smuzhiyun struct psb_intel_crtc_state *crtc_state;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun const struct gma_clock_funcs *clock_funcs;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun struct drm_pending_vblank_event *page_flip_event;
168*4882a593Smuzhiyun };
169*4882a593Smuzhiyun
170*4882a593Smuzhiyun #define to_gma_crtc(x) \
171*4882a593Smuzhiyun container_of(x, struct gma_crtc, base)
172*4882a593Smuzhiyun #define to_gma_connector(x) \
173*4882a593Smuzhiyun container_of(x, struct gma_connector, base)
174*4882a593Smuzhiyun #define to_gma_encoder(x) \
175*4882a593Smuzhiyun container_of(x, struct gma_encoder, base)
176*4882a593Smuzhiyun #define to_psb_intel_framebuffer(x) \
177*4882a593Smuzhiyun container_of(x, struct psb_intel_framebuffer, base)
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun struct psb_intel_i2c_chan *psb_intel_i2c_create(struct drm_device *dev,
180*4882a593Smuzhiyun const u32 reg, const char *name);
181*4882a593Smuzhiyun void psb_intel_i2c_destroy(struct psb_intel_i2c_chan *chan);
182*4882a593Smuzhiyun int psb_intel_ddc_get_modes(struct drm_connector *connector,
183*4882a593Smuzhiyun struct i2c_adapter *adapter);
184*4882a593Smuzhiyun extern bool psb_intel_ddc_probe(struct i2c_adapter *adapter);
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun extern void psb_intel_crtc_init(struct drm_device *dev, int pipe,
187*4882a593Smuzhiyun struct psb_intel_mode_device *mode_dev);
188*4882a593Smuzhiyun extern void psb_intel_crt_init(struct drm_device *dev);
189*4882a593Smuzhiyun extern bool psb_intel_sdvo_init(struct drm_device *dev, int output_device);
190*4882a593Smuzhiyun extern void psb_intel_dvo_init(struct drm_device *dev);
191*4882a593Smuzhiyun extern void psb_intel_tv_init(struct drm_device *dev);
192*4882a593Smuzhiyun extern void psb_intel_lvds_init(struct drm_device *dev,
193*4882a593Smuzhiyun struct psb_intel_mode_device *mode_dev);
194*4882a593Smuzhiyun extern void psb_intel_lvds_set_brightness(struct drm_device *dev, int level);
195*4882a593Smuzhiyun extern void oaktrail_lvds_init(struct drm_device *dev,
196*4882a593Smuzhiyun struct psb_intel_mode_device *mode_dev);
197*4882a593Smuzhiyun extern void oaktrail_wait_for_INTR_PKT_SENT(struct drm_device *dev);
198*4882a593Smuzhiyun extern void oaktrail_dsi_init(struct drm_device *dev,
199*4882a593Smuzhiyun struct psb_intel_mode_device *mode_dev);
200*4882a593Smuzhiyun extern void oaktrail_lvds_i2c_init(struct drm_encoder *encoder);
201*4882a593Smuzhiyun extern void mid_dsi_init(struct drm_device *dev,
202*4882a593Smuzhiyun struct psb_intel_mode_device *mode_dev, int dsi_num);
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun extern struct drm_encoder *gma_best_encoder(struct drm_connector *connector);
205*4882a593Smuzhiyun extern void gma_connector_attach_encoder(struct gma_connector *connector,
206*4882a593Smuzhiyun struct gma_encoder *encoder);
207*4882a593Smuzhiyun
gma_attached_encoder(struct drm_connector * connector)208*4882a593Smuzhiyun static inline struct gma_encoder *gma_attached_encoder(
209*4882a593Smuzhiyun struct drm_connector *connector)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun return to_gma_connector(connector)->encoder;
212*4882a593Smuzhiyun }
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun extern struct drm_display_mode *psb_intel_crtc_mode_get(struct drm_device *dev,
215*4882a593Smuzhiyun struct drm_crtc *crtc);
216*4882a593Smuzhiyun extern struct drm_crtc *psb_intel_get_crtc_from_pipe(struct drm_device *dev,
217*4882a593Smuzhiyun int pipe);
218*4882a593Smuzhiyun extern struct drm_connector *psb_intel_sdvo_find(struct drm_device *dev,
219*4882a593Smuzhiyun int sdvoB);
220*4882a593Smuzhiyun extern int psb_intel_sdvo_supports_hotplug(struct drm_connector *connector);
221*4882a593Smuzhiyun extern void psb_intel_sdvo_set_hotplug(struct drm_connector *connector,
222*4882a593Smuzhiyun int enable);
223*4882a593Smuzhiyun extern int intelfb_probe(struct drm_device *dev);
224*4882a593Smuzhiyun extern int intelfb_remove(struct drm_device *dev,
225*4882a593Smuzhiyun struct drm_framebuffer *fb);
226*4882a593Smuzhiyun extern bool psb_intel_lvds_mode_fixup(struct drm_encoder *encoder,
227*4882a593Smuzhiyun const struct drm_display_mode *mode,
228*4882a593Smuzhiyun struct drm_display_mode *adjusted_mode);
229*4882a593Smuzhiyun extern enum drm_mode_status psb_intel_lvds_mode_valid(struct drm_connector *connector,
230*4882a593Smuzhiyun struct drm_display_mode *mode);
231*4882a593Smuzhiyun extern int psb_intel_lvds_set_property(struct drm_connector *connector,
232*4882a593Smuzhiyun struct drm_property *property,
233*4882a593Smuzhiyun uint64_t value);
234*4882a593Smuzhiyun extern void psb_intel_lvds_destroy(struct drm_connector *connector);
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun /* intel_gmbus.c */
237*4882a593Smuzhiyun extern void gma_intel_i2c_reset(struct drm_device *dev);
238*4882a593Smuzhiyun extern int gma_intel_setup_gmbus(struct drm_device *dev);
239*4882a593Smuzhiyun extern void gma_intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed);
240*4882a593Smuzhiyun extern void gma_intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit);
241*4882a593Smuzhiyun extern void gma_intel_teardown_gmbus(struct drm_device *dev);
242*4882a593Smuzhiyun
243*4882a593Smuzhiyun /* DP support */
244*4882a593Smuzhiyun extern void cdv_intel_dp_init(struct drm_device *dev, struct psb_intel_mode_device *mode_dev, int output_reg);
245*4882a593Smuzhiyun extern void cdv_intel_dp_set_m_n(struct drm_crtc *crtc,
246*4882a593Smuzhiyun struct drm_display_mode *mode,
247*4882a593Smuzhiyun struct drm_display_mode *adjusted_mode);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun extern void psb_intel_attach_force_audio_property(struct drm_connector *connector);
250*4882a593Smuzhiyun extern void psb_intel_attach_broadcast_rgb_property(struct drm_connector *connector);
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun extern int cdv_sb_read(struct drm_device *dev, u32 reg, u32 *val);
253*4882a593Smuzhiyun extern int cdv_sb_write(struct drm_device *dev, u32 reg, u32 val);
254*4882a593Smuzhiyun extern void cdv_sb_reset(struct drm_device *dev);
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun extern void cdv_intel_attach_force_audio_property(struct drm_connector *connector);
257*4882a593Smuzhiyun extern void cdv_intel_attach_broadcast_rgb_property(struct drm_connector *connector);
258*4882a593Smuzhiyun
259*4882a593Smuzhiyun #endif /* __INTEL_DRV_H__ */
260