1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /************************************************************************** 3*4882a593Smuzhiyun * Copyright (c) 2007-2011, Intel Corporation. 4*4882a593Smuzhiyun * All Rights Reserved. 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun **************************************************************************/ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef __MMU_H 9*4882a593Smuzhiyun #define __MMU_H 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun struct psb_mmu_driver { 12*4882a593Smuzhiyun /* protects driver- and pd structures. Always take in read mode 13*4882a593Smuzhiyun * before taking the page table spinlock. 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun struct rw_semaphore sem; 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* protects page tables, directory tables and pt tables. 18*4882a593Smuzhiyun * and pt structures. 19*4882a593Smuzhiyun */ 20*4882a593Smuzhiyun spinlock_t lock; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun atomic_t needs_tlbflush; 23*4882a593Smuzhiyun atomic_t *msvdx_mmu_invaldc; 24*4882a593Smuzhiyun struct psb_mmu_pd *default_pd; 25*4882a593Smuzhiyun uint32_t bif_ctrl; 26*4882a593Smuzhiyun int has_clflush; 27*4882a593Smuzhiyun int clflush_add; 28*4882a593Smuzhiyun unsigned long clflush_mask; 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct drm_device *dev; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct psb_mmu_pd; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct psb_mmu_pt { 36*4882a593Smuzhiyun struct psb_mmu_pd *pd; 37*4882a593Smuzhiyun uint32_t index; 38*4882a593Smuzhiyun uint32_t count; 39*4882a593Smuzhiyun struct page *p; 40*4882a593Smuzhiyun uint32_t *v; 41*4882a593Smuzhiyun }; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct psb_mmu_pd { 44*4882a593Smuzhiyun struct psb_mmu_driver *driver; 45*4882a593Smuzhiyun int hw_context; 46*4882a593Smuzhiyun struct psb_mmu_pt **tables; 47*4882a593Smuzhiyun struct page *p; 48*4882a593Smuzhiyun struct page *dummy_pt; 49*4882a593Smuzhiyun struct page *dummy_page; 50*4882a593Smuzhiyun uint32_t pd_mask; 51*4882a593Smuzhiyun uint32_t invalid_pde; 52*4882a593Smuzhiyun uint32_t invalid_pte; 53*4882a593Smuzhiyun }; 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun extern struct psb_mmu_driver *psb_mmu_driver_init(struct drm_device *dev, 56*4882a593Smuzhiyun int trap_pagefaults, 57*4882a593Smuzhiyun int invalid_type, 58*4882a593Smuzhiyun atomic_t *msvdx_mmu_invaldc); 59*4882a593Smuzhiyun extern void psb_mmu_driver_takedown(struct psb_mmu_driver *driver); 60*4882a593Smuzhiyun extern struct psb_mmu_pd *psb_mmu_get_default_pd(struct psb_mmu_driver 61*4882a593Smuzhiyun *driver); 62*4882a593Smuzhiyun extern struct psb_mmu_pd *psb_mmu_alloc_pd(struct psb_mmu_driver *driver, 63*4882a593Smuzhiyun int trap_pagefaults, 64*4882a593Smuzhiyun int invalid_type); 65*4882a593Smuzhiyun extern void psb_mmu_free_pagedir(struct psb_mmu_pd *pd); 66*4882a593Smuzhiyun extern void psb_mmu_flush(struct psb_mmu_driver *driver); 67*4882a593Smuzhiyun extern void psb_mmu_remove_pfn_sequence(struct psb_mmu_pd *pd, 68*4882a593Smuzhiyun unsigned long address, 69*4882a593Smuzhiyun uint32_t num_pages); 70*4882a593Smuzhiyun extern int psb_mmu_insert_pfn_sequence(struct psb_mmu_pd *pd, 71*4882a593Smuzhiyun uint32_t start_pfn, 72*4882a593Smuzhiyun unsigned long address, 73*4882a593Smuzhiyun uint32_t num_pages, int type); 74*4882a593Smuzhiyun extern int psb_mmu_virtual_to_pfn(struct psb_mmu_pd *pd, uint32_t virtual, 75*4882a593Smuzhiyun unsigned long *pfn); 76*4882a593Smuzhiyun extern void psb_mmu_set_pd_context(struct psb_mmu_pd *pd, int hw_context); 77*4882a593Smuzhiyun extern int psb_mmu_insert_pages(struct psb_mmu_pd *pd, struct page **pages, 78*4882a593Smuzhiyun unsigned long address, uint32_t num_pages, 79*4882a593Smuzhiyun uint32_t desired_tile_stride, 80*4882a593Smuzhiyun uint32_t hw_tile_stride, int type); 81*4882a593Smuzhiyun extern void psb_mmu_remove_pages(struct psb_mmu_pd *pd, 82*4882a593Smuzhiyun unsigned long address, uint32_t num_pages, 83*4882a593Smuzhiyun uint32_t desired_tile_stride, 84*4882a593Smuzhiyun uint32_t hw_tile_stride); 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #endif 87