1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /**************************************************************************
3*4882a593Smuzhiyun * Copyright (c) 2011, Intel Corporation.
4*4882a593Smuzhiyun * All Rights Reserved.
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun **************************************************************************/
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include "psb_drv.h"
9*4882a593Smuzhiyun
gma_get_core_freq(struct drm_device * dev)10*4882a593Smuzhiyun void gma_get_core_freq(struct drm_device *dev)
11*4882a593Smuzhiyun {
12*4882a593Smuzhiyun uint32_t clock;
13*4882a593Smuzhiyun struct pci_dev *pci_root =
14*4882a593Smuzhiyun pci_get_domain_bus_and_slot(pci_domain_nr(dev->pdev->bus),
15*4882a593Smuzhiyun 0, 0);
16*4882a593Smuzhiyun struct drm_psb_private *dev_priv = dev->dev_private;
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun /*pci_write_config_dword(pci_root, 0xD4, 0x00C32004);*/
19*4882a593Smuzhiyun /*pci_write_config_dword(pci_root, 0xD0, 0xE0033000);*/
20*4882a593Smuzhiyun
21*4882a593Smuzhiyun pci_write_config_dword(pci_root, 0xD0, 0xD0050300);
22*4882a593Smuzhiyun pci_read_config_dword(pci_root, 0xD4, &clock);
23*4882a593Smuzhiyun pci_dev_put(pci_root);
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun switch (clock & 0x07) {
26*4882a593Smuzhiyun case 0:
27*4882a593Smuzhiyun dev_priv->core_freq = 100;
28*4882a593Smuzhiyun break;
29*4882a593Smuzhiyun case 1:
30*4882a593Smuzhiyun dev_priv->core_freq = 133;
31*4882a593Smuzhiyun break;
32*4882a593Smuzhiyun case 2:
33*4882a593Smuzhiyun dev_priv->core_freq = 150;
34*4882a593Smuzhiyun break;
35*4882a593Smuzhiyun case 3:
36*4882a593Smuzhiyun dev_priv->core_freq = 178;
37*4882a593Smuzhiyun break;
38*4882a593Smuzhiyun case 4:
39*4882a593Smuzhiyun dev_priv->core_freq = 200;
40*4882a593Smuzhiyun break;
41*4882a593Smuzhiyun case 5:
42*4882a593Smuzhiyun case 6:
43*4882a593Smuzhiyun case 7:
44*4882a593Smuzhiyun dev_priv->core_freq = 266;
45*4882a593Smuzhiyun break;
46*4882a593Smuzhiyun default:
47*4882a593Smuzhiyun dev_priv->core_freq = 0;
48*4882a593Smuzhiyun }
49*4882a593Smuzhiyun }
50