1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright © 2006-2011 Intel Corporation
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice (including the next
12*4882a593Smuzhiyun * paragraph) shall be included in all copies or substantial portions of the
13*4882a593Smuzhiyun * Software.
14*4882a593Smuzhiyun *
15*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18*4882a593Smuzhiyun * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19*4882a593Smuzhiyun * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20*4882a593Smuzhiyun * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21*4882a593Smuzhiyun * DEALINGS IN THE SOFTWARE.
22*4882a593Smuzhiyun *
23*4882a593Smuzhiyun * Authors:
24*4882a593Smuzhiyun * jim liu <jim.liu@intel.com>
25*4882a593Smuzhiyun *
26*4882a593Smuzhiyun * FIXME:
27*4882a593Smuzhiyun * We should probably make this generic and share it with Medfield
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun #include <linux/pm_runtime.h>
31*4882a593Smuzhiyun
32*4882a593Smuzhiyun #include <drm/drm.h>
33*4882a593Smuzhiyun #include <drm/drm_crtc.h>
34*4882a593Smuzhiyun #include <drm/drm_edid.h>
35*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
36*4882a593Smuzhiyun
37*4882a593Smuzhiyun #include "cdv_device.h"
38*4882a593Smuzhiyun #include "psb_drv.h"
39*4882a593Smuzhiyun #include "psb_intel_drv.h"
40*4882a593Smuzhiyun #include "psb_intel_reg.h"
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun /* hdmi control bits */
43*4882a593Smuzhiyun #define HDMI_NULL_PACKETS_DURING_VSYNC (1 << 9)
44*4882a593Smuzhiyun #define HDMI_BORDER_ENABLE (1 << 7)
45*4882a593Smuzhiyun #define HDMI_AUDIO_ENABLE (1 << 6)
46*4882a593Smuzhiyun #define HDMI_VSYNC_ACTIVE_HIGH (1 << 4)
47*4882a593Smuzhiyun #define HDMI_HSYNC_ACTIVE_HIGH (1 << 3)
48*4882a593Smuzhiyun /* hdmi-b control bits */
49*4882a593Smuzhiyun #define HDMIB_PIPE_B_SELECT (1 << 30)
50*4882a593Smuzhiyun
51*4882a593Smuzhiyun
52*4882a593Smuzhiyun struct mid_intel_hdmi_priv {
53*4882a593Smuzhiyun u32 hdmi_reg;
54*4882a593Smuzhiyun u32 save_HDMIB;
55*4882a593Smuzhiyun bool has_hdmi_sink;
56*4882a593Smuzhiyun bool has_hdmi_audio;
57*4882a593Smuzhiyun /* Should set this when detect hotplug */
58*4882a593Smuzhiyun bool hdmi_device_connected;
59*4882a593Smuzhiyun struct mdfld_hdmi_i2c *i2c_bus;
60*4882a593Smuzhiyun struct i2c_adapter *hdmi_i2c_adapter; /* for control functions */
61*4882a593Smuzhiyun struct drm_device *dev;
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
cdv_hdmi_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)64*4882a593Smuzhiyun static void cdv_hdmi_mode_set(struct drm_encoder *encoder,
65*4882a593Smuzhiyun struct drm_display_mode *mode,
66*4882a593Smuzhiyun struct drm_display_mode *adjusted_mode)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
69*4882a593Smuzhiyun struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
70*4882a593Smuzhiyun struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;
71*4882a593Smuzhiyun u32 hdmib;
72*4882a593Smuzhiyun struct drm_crtc *crtc = encoder->crtc;
73*4882a593Smuzhiyun struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
74*4882a593Smuzhiyun
75*4882a593Smuzhiyun hdmib = (2 << 10);
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
78*4882a593Smuzhiyun hdmib |= HDMI_VSYNC_ACTIVE_HIGH;
79*4882a593Smuzhiyun if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
80*4882a593Smuzhiyun hdmib |= HDMI_HSYNC_ACTIVE_HIGH;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun if (gma_crtc->pipe == 1)
83*4882a593Smuzhiyun hdmib |= HDMIB_PIPE_B_SELECT;
84*4882a593Smuzhiyun
85*4882a593Smuzhiyun if (hdmi_priv->has_hdmi_audio) {
86*4882a593Smuzhiyun hdmib |= HDMI_AUDIO_ENABLE;
87*4882a593Smuzhiyun hdmib |= HDMI_NULL_PACKETS_DURING_VSYNC;
88*4882a593Smuzhiyun }
89*4882a593Smuzhiyun
90*4882a593Smuzhiyun REG_WRITE(hdmi_priv->hdmi_reg, hdmib);
91*4882a593Smuzhiyun REG_READ(hdmi_priv->hdmi_reg);
92*4882a593Smuzhiyun }
93*4882a593Smuzhiyun
cdv_hdmi_dpms(struct drm_encoder * encoder,int mode)94*4882a593Smuzhiyun static void cdv_hdmi_dpms(struct drm_encoder *encoder, int mode)
95*4882a593Smuzhiyun {
96*4882a593Smuzhiyun struct drm_device *dev = encoder->dev;
97*4882a593Smuzhiyun struct gma_encoder *gma_encoder = to_gma_encoder(encoder);
98*4882a593Smuzhiyun struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;
99*4882a593Smuzhiyun u32 hdmib;
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun hdmib = REG_READ(hdmi_priv->hdmi_reg);
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun if (mode != DRM_MODE_DPMS_ON)
104*4882a593Smuzhiyun REG_WRITE(hdmi_priv->hdmi_reg, hdmib & ~HDMIB_PORT_EN);
105*4882a593Smuzhiyun else
106*4882a593Smuzhiyun REG_WRITE(hdmi_priv->hdmi_reg, hdmib | HDMIB_PORT_EN);
107*4882a593Smuzhiyun REG_READ(hdmi_priv->hdmi_reg);
108*4882a593Smuzhiyun }
109*4882a593Smuzhiyun
cdv_hdmi_save(struct drm_connector * connector)110*4882a593Smuzhiyun static void cdv_hdmi_save(struct drm_connector *connector)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
113*4882a593Smuzhiyun struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
114*4882a593Smuzhiyun struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun hdmi_priv->save_HDMIB = REG_READ(hdmi_priv->hdmi_reg);
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
cdv_hdmi_restore(struct drm_connector * connector)119*4882a593Smuzhiyun static void cdv_hdmi_restore(struct drm_connector *connector)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
122*4882a593Smuzhiyun struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
123*4882a593Smuzhiyun struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;
124*4882a593Smuzhiyun
125*4882a593Smuzhiyun REG_WRITE(hdmi_priv->hdmi_reg, hdmi_priv->save_HDMIB);
126*4882a593Smuzhiyun REG_READ(hdmi_priv->hdmi_reg);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun
cdv_hdmi_detect(struct drm_connector * connector,bool force)129*4882a593Smuzhiyun static enum drm_connector_status cdv_hdmi_detect(
130*4882a593Smuzhiyun struct drm_connector *connector, bool force)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
133*4882a593Smuzhiyun struct mid_intel_hdmi_priv *hdmi_priv = gma_encoder->dev_priv;
134*4882a593Smuzhiyun struct edid *edid = NULL;
135*4882a593Smuzhiyun enum drm_connector_status status = connector_status_disconnected;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun edid = drm_get_edid(connector, &gma_encoder->i2c_bus->adapter);
138*4882a593Smuzhiyun
139*4882a593Smuzhiyun hdmi_priv->has_hdmi_sink = false;
140*4882a593Smuzhiyun hdmi_priv->has_hdmi_audio = false;
141*4882a593Smuzhiyun if (edid) {
142*4882a593Smuzhiyun if (edid->input & DRM_EDID_INPUT_DIGITAL) {
143*4882a593Smuzhiyun status = connector_status_connected;
144*4882a593Smuzhiyun hdmi_priv->has_hdmi_sink =
145*4882a593Smuzhiyun drm_detect_hdmi_monitor(edid);
146*4882a593Smuzhiyun hdmi_priv->has_hdmi_audio =
147*4882a593Smuzhiyun drm_detect_monitor_audio(edid);
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun kfree(edid);
150*4882a593Smuzhiyun }
151*4882a593Smuzhiyun return status;
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun
cdv_hdmi_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t value)154*4882a593Smuzhiyun static int cdv_hdmi_set_property(struct drm_connector *connector,
155*4882a593Smuzhiyun struct drm_property *property,
156*4882a593Smuzhiyun uint64_t value)
157*4882a593Smuzhiyun {
158*4882a593Smuzhiyun struct drm_encoder *encoder = connector->encoder;
159*4882a593Smuzhiyun
160*4882a593Smuzhiyun if (!strcmp(property->name, "scaling mode") && encoder) {
161*4882a593Smuzhiyun struct gma_crtc *crtc = to_gma_crtc(encoder->crtc);
162*4882a593Smuzhiyun bool centre;
163*4882a593Smuzhiyun uint64_t curValue;
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun if (!crtc)
166*4882a593Smuzhiyun return -1;
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun switch (value) {
169*4882a593Smuzhiyun case DRM_MODE_SCALE_FULLSCREEN:
170*4882a593Smuzhiyun break;
171*4882a593Smuzhiyun case DRM_MODE_SCALE_NO_SCALE:
172*4882a593Smuzhiyun break;
173*4882a593Smuzhiyun case DRM_MODE_SCALE_ASPECT:
174*4882a593Smuzhiyun break;
175*4882a593Smuzhiyun default:
176*4882a593Smuzhiyun return -1;
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun
179*4882a593Smuzhiyun if (drm_object_property_get_value(&connector->base,
180*4882a593Smuzhiyun property, &curValue))
181*4882a593Smuzhiyun return -1;
182*4882a593Smuzhiyun
183*4882a593Smuzhiyun if (curValue == value)
184*4882a593Smuzhiyun return 0;
185*4882a593Smuzhiyun
186*4882a593Smuzhiyun if (drm_object_property_set_value(&connector->base,
187*4882a593Smuzhiyun property, value))
188*4882a593Smuzhiyun return -1;
189*4882a593Smuzhiyun
190*4882a593Smuzhiyun centre = (curValue == DRM_MODE_SCALE_NO_SCALE) ||
191*4882a593Smuzhiyun (value == DRM_MODE_SCALE_NO_SCALE);
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun if (crtc->saved_mode.hdisplay != 0 &&
194*4882a593Smuzhiyun crtc->saved_mode.vdisplay != 0) {
195*4882a593Smuzhiyun if (centre) {
196*4882a593Smuzhiyun if (!drm_crtc_helper_set_mode(encoder->crtc, &crtc->saved_mode,
197*4882a593Smuzhiyun encoder->crtc->x, encoder->crtc->y, encoder->crtc->primary->fb))
198*4882a593Smuzhiyun return -1;
199*4882a593Smuzhiyun } else {
200*4882a593Smuzhiyun const struct drm_encoder_helper_funcs *helpers
201*4882a593Smuzhiyun = encoder->helper_private;
202*4882a593Smuzhiyun helpers->mode_set(encoder, &crtc->saved_mode,
203*4882a593Smuzhiyun &crtc->saved_adjusted_mode);
204*4882a593Smuzhiyun }
205*4882a593Smuzhiyun }
206*4882a593Smuzhiyun }
207*4882a593Smuzhiyun return 0;
208*4882a593Smuzhiyun }
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun /*
211*4882a593Smuzhiyun * Return the list of HDMI DDC modes if available.
212*4882a593Smuzhiyun */
cdv_hdmi_get_modes(struct drm_connector * connector)213*4882a593Smuzhiyun static int cdv_hdmi_get_modes(struct drm_connector *connector)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
216*4882a593Smuzhiyun struct edid *edid = NULL;
217*4882a593Smuzhiyun int ret = 0;
218*4882a593Smuzhiyun
219*4882a593Smuzhiyun edid = drm_get_edid(connector, &gma_encoder->i2c_bus->adapter);
220*4882a593Smuzhiyun if (edid) {
221*4882a593Smuzhiyun drm_connector_update_edid_property(connector, edid);
222*4882a593Smuzhiyun ret = drm_add_edid_modes(connector, edid);
223*4882a593Smuzhiyun kfree(edid);
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun return ret;
226*4882a593Smuzhiyun }
227*4882a593Smuzhiyun
cdv_hdmi_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)228*4882a593Smuzhiyun static enum drm_mode_status cdv_hdmi_mode_valid(struct drm_connector *connector,
229*4882a593Smuzhiyun struct drm_display_mode *mode)
230*4882a593Smuzhiyun {
231*4882a593Smuzhiyun if (mode->clock > 165000)
232*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
233*4882a593Smuzhiyun if (mode->clock < 20000)
234*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun /* just in case */
237*4882a593Smuzhiyun if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
238*4882a593Smuzhiyun return MODE_NO_DBLESCAN;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun /* just in case */
241*4882a593Smuzhiyun if (mode->flags & DRM_MODE_FLAG_INTERLACE)
242*4882a593Smuzhiyun return MODE_NO_INTERLACE;
243*4882a593Smuzhiyun
244*4882a593Smuzhiyun return MODE_OK;
245*4882a593Smuzhiyun }
246*4882a593Smuzhiyun
cdv_hdmi_destroy(struct drm_connector * connector)247*4882a593Smuzhiyun static void cdv_hdmi_destroy(struct drm_connector *connector)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun psb_intel_i2c_destroy(gma_encoder->i2c_bus);
252*4882a593Smuzhiyun drm_connector_unregister(connector);
253*4882a593Smuzhiyun drm_connector_cleanup(connector);
254*4882a593Smuzhiyun kfree(connector);
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun
257*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs cdv_hdmi_helper_funcs = {
258*4882a593Smuzhiyun .dpms = cdv_hdmi_dpms,
259*4882a593Smuzhiyun .prepare = gma_encoder_prepare,
260*4882a593Smuzhiyun .mode_set = cdv_hdmi_mode_set,
261*4882a593Smuzhiyun .commit = gma_encoder_commit,
262*4882a593Smuzhiyun };
263*4882a593Smuzhiyun
264*4882a593Smuzhiyun static const struct drm_connector_helper_funcs
265*4882a593Smuzhiyun cdv_hdmi_connector_helper_funcs = {
266*4882a593Smuzhiyun .get_modes = cdv_hdmi_get_modes,
267*4882a593Smuzhiyun .mode_valid = cdv_hdmi_mode_valid,
268*4882a593Smuzhiyun .best_encoder = gma_best_encoder,
269*4882a593Smuzhiyun };
270*4882a593Smuzhiyun
271*4882a593Smuzhiyun static const struct drm_connector_funcs cdv_hdmi_connector_funcs = {
272*4882a593Smuzhiyun .dpms = drm_helper_connector_dpms,
273*4882a593Smuzhiyun .detect = cdv_hdmi_detect,
274*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
275*4882a593Smuzhiyun .set_property = cdv_hdmi_set_property,
276*4882a593Smuzhiyun .destroy = cdv_hdmi_destroy,
277*4882a593Smuzhiyun };
278*4882a593Smuzhiyun
cdv_hdmi_init(struct drm_device * dev,struct psb_intel_mode_device * mode_dev,int reg)279*4882a593Smuzhiyun void cdv_hdmi_init(struct drm_device *dev,
280*4882a593Smuzhiyun struct psb_intel_mode_device *mode_dev, int reg)
281*4882a593Smuzhiyun {
282*4882a593Smuzhiyun struct gma_encoder *gma_encoder;
283*4882a593Smuzhiyun struct gma_connector *gma_connector;
284*4882a593Smuzhiyun struct drm_connector *connector;
285*4882a593Smuzhiyun struct drm_encoder *encoder;
286*4882a593Smuzhiyun struct mid_intel_hdmi_priv *hdmi_priv;
287*4882a593Smuzhiyun int ddc_bus;
288*4882a593Smuzhiyun
289*4882a593Smuzhiyun gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun if (!gma_encoder)
292*4882a593Smuzhiyun return;
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun gma_connector = kzalloc(sizeof(struct gma_connector),
295*4882a593Smuzhiyun GFP_KERNEL);
296*4882a593Smuzhiyun
297*4882a593Smuzhiyun if (!gma_connector)
298*4882a593Smuzhiyun goto err_connector;
299*4882a593Smuzhiyun
300*4882a593Smuzhiyun hdmi_priv = kzalloc(sizeof(struct mid_intel_hdmi_priv), GFP_KERNEL);
301*4882a593Smuzhiyun
302*4882a593Smuzhiyun if (!hdmi_priv)
303*4882a593Smuzhiyun goto err_priv;
304*4882a593Smuzhiyun
305*4882a593Smuzhiyun connector = &gma_connector->base;
306*4882a593Smuzhiyun connector->polled = DRM_CONNECTOR_POLL_HPD;
307*4882a593Smuzhiyun gma_connector->save = cdv_hdmi_save;
308*4882a593Smuzhiyun gma_connector->restore = cdv_hdmi_restore;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun encoder = &gma_encoder->base;
311*4882a593Smuzhiyun drm_connector_init(dev, connector,
312*4882a593Smuzhiyun &cdv_hdmi_connector_funcs,
313*4882a593Smuzhiyun DRM_MODE_CONNECTOR_DVID);
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_TMDS);
316*4882a593Smuzhiyun
317*4882a593Smuzhiyun gma_connector_attach_encoder(gma_connector, gma_encoder);
318*4882a593Smuzhiyun gma_encoder->type = INTEL_OUTPUT_HDMI;
319*4882a593Smuzhiyun hdmi_priv->hdmi_reg = reg;
320*4882a593Smuzhiyun hdmi_priv->has_hdmi_sink = false;
321*4882a593Smuzhiyun gma_encoder->dev_priv = hdmi_priv;
322*4882a593Smuzhiyun
323*4882a593Smuzhiyun drm_encoder_helper_add(encoder, &cdv_hdmi_helper_funcs);
324*4882a593Smuzhiyun drm_connector_helper_add(connector,
325*4882a593Smuzhiyun &cdv_hdmi_connector_helper_funcs);
326*4882a593Smuzhiyun connector->display_info.subpixel_order = SubPixelHorizontalRGB;
327*4882a593Smuzhiyun connector->interlace_allowed = false;
328*4882a593Smuzhiyun connector->doublescan_allowed = false;
329*4882a593Smuzhiyun
330*4882a593Smuzhiyun drm_object_attach_property(&connector->base,
331*4882a593Smuzhiyun dev->mode_config.scaling_mode_property,
332*4882a593Smuzhiyun DRM_MODE_SCALE_FULLSCREEN);
333*4882a593Smuzhiyun
334*4882a593Smuzhiyun switch (reg) {
335*4882a593Smuzhiyun case SDVOB:
336*4882a593Smuzhiyun ddc_bus = GPIOE;
337*4882a593Smuzhiyun gma_encoder->ddi_select = DDI0_SELECT;
338*4882a593Smuzhiyun break;
339*4882a593Smuzhiyun case SDVOC:
340*4882a593Smuzhiyun ddc_bus = GPIOD;
341*4882a593Smuzhiyun gma_encoder->ddi_select = DDI1_SELECT;
342*4882a593Smuzhiyun break;
343*4882a593Smuzhiyun default:
344*4882a593Smuzhiyun DRM_ERROR("unknown reg 0x%x for HDMI\n", reg);
345*4882a593Smuzhiyun goto failed_ddc;
346*4882a593Smuzhiyun break;
347*4882a593Smuzhiyun }
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun gma_encoder->i2c_bus = psb_intel_i2c_create(dev,
350*4882a593Smuzhiyun ddc_bus, (reg == SDVOB) ? "HDMIB" : "HDMIC");
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun if (!gma_encoder->i2c_bus) {
353*4882a593Smuzhiyun dev_err(dev->dev, "No ddc adapter available!\n");
354*4882a593Smuzhiyun goto failed_ddc;
355*4882a593Smuzhiyun }
356*4882a593Smuzhiyun
357*4882a593Smuzhiyun hdmi_priv->hdmi_i2c_adapter = &(gma_encoder->i2c_bus->adapter);
358*4882a593Smuzhiyun hdmi_priv->dev = dev;
359*4882a593Smuzhiyun drm_connector_register(connector);
360*4882a593Smuzhiyun return;
361*4882a593Smuzhiyun
362*4882a593Smuzhiyun failed_ddc:
363*4882a593Smuzhiyun drm_encoder_cleanup(encoder);
364*4882a593Smuzhiyun drm_connector_cleanup(connector);
365*4882a593Smuzhiyun err_priv:
366*4882a593Smuzhiyun kfree(gma_connector);
367*4882a593Smuzhiyun err_connector:
368*4882a593Smuzhiyun kfree(gma_encoder);
369*4882a593Smuzhiyun }
370