xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/gma500/cdv_intel_crt.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright © 2006-2007 Intel Corporation
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * The above copyright notice and this permission notice (including the next
12*4882a593Smuzhiyun  * paragraph) shall be included in all copies or substantial portions of the
13*4882a593Smuzhiyun  * Software.
14*4882a593Smuzhiyun  *
15*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18*4882a593Smuzhiyun  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19*4882a593Smuzhiyun  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20*4882a593Smuzhiyun  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21*4882a593Smuzhiyun  * DEALINGS IN THE SOFTWARE.
22*4882a593Smuzhiyun  *
23*4882a593Smuzhiyun  * Authors:
24*4882a593Smuzhiyun  *	Eric Anholt <eric@anholt.net>
25*4882a593Smuzhiyun  */
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun #include <linux/delay.h>
28*4882a593Smuzhiyun #include <linux/i2c.h>
29*4882a593Smuzhiyun #include <linux/pm_runtime.h>
30*4882a593Smuzhiyun 
31*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun #include "cdv_device.h"
34*4882a593Smuzhiyun #include "intel_bios.h"
35*4882a593Smuzhiyun #include "power.h"
36*4882a593Smuzhiyun #include "psb_drv.h"
37*4882a593Smuzhiyun #include "psb_intel_drv.h"
38*4882a593Smuzhiyun #include "psb_intel_reg.h"
39*4882a593Smuzhiyun 
40*4882a593Smuzhiyun 
cdv_intel_crt_dpms(struct drm_encoder * encoder,int mode)41*4882a593Smuzhiyun static void cdv_intel_crt_dpms(struct drm_encoder *encoder, int mode)
42*4882a593Smuzhiyun {
43*4882a593Smuzhiyun 	struct drm_device *dev = encoder->dev;
44*4882a593Smuzhiyun 	u32 temp, reg;
45*4882a593Smuzhiyun 	reg = ADPA;
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 	temp = REG_READ(reg);
48*4882a593Smuzhiyun 	temp &= ~(ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE);
49*4882a593Smuzhiyun 	temp &= ~ADPA_DAC_ENABLE;
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun 	switch (mode) {
52*4882a593Smuzhiyun 	case DRM_MODE_DPMS_ON:
53*4882a593Smuzhiyun 		temp |= ADPA_DAC_ENABLE;
54*4882a593Smuzhiyun 		break;
55*4882a593Smuzhiyun 	case DRM_MODE_DPMS_STANDBY:
56*4882a593Smuzhiyun 		temp |= ADPA_DAC_ENABLE | ADPA_HSYNC_CNTL_DISABLE;
57*4882a593Smuzhiyun 		break;
58*4882a593Smuzhiyun 	case DRM_MODE_DPMS_SUSPEND:
59*4882a593Smuzhiyun 		temp |= ADPA_DAC_ENABLE | ADPA_VSYNC_CNTL_DISABLE;
60*4882a593Smuzhiyun 		break;
61*4882a593Smuzhiyun 	case DRM_MODE_DPMS_OFF:
62*4882a593Smuzhiyun 		temp |= ADPA_HSYNC_CNTL_DISABLE | ADPA_VSYNC_CNTL_DISABLE;
63*4882a593Smuzhiyun 		break;
64*4882a593Smuzhiyun 	}
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun 	REG_WRITE(reg, temp);
67*4882a593Smuzhiyun }
68*4882a593Smuzhiyun 
cdv_intel_crt_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)69*4882a593Smuzhiyun static enum drm_mode_status cdv_intel_crt_mode_valid(struct drm_connector *connector,
70*4882a593Smuzhiyun 				struct drm_display_mode *mode)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun 	if (mode->flags & DRM_MODE_FLAG_DBLSCAN)
73*4882a593Smuzhiyun 		return MODE_NO_DBLESCAN;
74*4882a593Smuzhiyun 
75*4882a593Smuzhiyun 	/* The lowest clock for CDV is 20000KHz */
76*4882a593Smuzhiyun 	if (mode->clock < 20000)
77*4882a593Smuzhiyun 		return MODE_CLOCK_LOW;
78*4882a593Smuzhiyun 
79*4882a593Smuzhiyun 	/* The max clock for CDV is 355 instead of 400 */
80*4882a593Smuzhiyun 	if (mode->clock > 355000)
81*4882a593Smuzhiyun 		return MODE_CLOCK_HIGH;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	return MODE_OK;
84*4882a593Smuzhiyun }
85*4882a593Smuzhiyun 
cdv_intel_crt_mode_set(struct drm_encoder * encoder,struct drm_display_mode * mode,struct drm_display_mode * adjusted_mode)86*4882a593Smuzhiyun static void cdv_intel_crt_mode_set(struct drm_encoder *encoder,
87*4882a593Smuzhiyun 			       struct drm_display_mode *mode,
88*4882a593Smuzhiyun 			       struct drm_display_mode *adjusted_mode)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun 
91*4882a593Smuzhiyun 	struct drm_device *dev = encoder->dev;
92*4882a593Smuzhiyun 	struct drm_crtc *crtc = encoder->crtc;
93*4882a593Smuzhiyun 	struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
94*4882a593Smuzhiyun 	int dpll_md_reg;
95*4882a593Smuzhiyun 	u32 adpa, dpll_md;
96*4882a593Smuzhiyun 	u32 adpa_reg;
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun 	if (gma_crtc->pipe == 0)
99*4882a593Smuzhiyun 		dpll_md_reg = DPLL_A_MD;
100*4882a593Smuzhiyun 	else
101*4882a593Smuzhiyun 		dpll_md_reg = DPLL_B_MD;
102*4882a593Smuzhiyun 
103*4882a593Smuzhiyun 	adpa_reg = ADPA;
104*4882a593Smuzhiyun 
105*4882a593Smuzhiyun 	/*
106*4882a593Smuzhiyun 	 * Disable separate mode multiplier used when cloning SDVO to CRT
107*4882a593Smuzhiyun 	 * XXX this needs to be adjusted when we really are cloning
108*4882a593Smuzhiyun 	 */
109*4882a593Smuzhiyun 	{
110*4882a593Smuzhiyun 		dpll_md = REG_READ(dpll_md_reg);
111*4882a593Smuzhiyun 		REG_WRITE(dpll_md_reg,
112*4882a593Smuzhiyun 			   dpll_md & ~DPLL_MD_UDI_MULTIPLIER_MASK);
113*4882a593Smuzhiyun 	}
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun 	adpa = 0;
116*4882a593Smuzhiyun 	if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC)
117*4882a593Smuzhiyun 		adpa |= ADPA_HSYNC_ACTIVE_HIGH;
118*4882a593Smuzhiyun 	if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC)
119*4882a593Smuzhiyun 		adpa |= ADPA_VSYNC_ACTIVE_HIGH;
120*4882a593Smuzhiyun 
121*4882a593Smuzhiyun 	if (gma_crtc->pipe == 0)
122*4882a593Smuzhiyun 		adpa |= ADPA_PIPE_A_SELECT;
123*4882a593Smuzhiyun 	else
124*4882a593Smuzhiyun 		adpa |= ADPA_PIPE_B_SELECT;
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun 	REG_WRITE(adpa_reg, adpa);
127*4882a593Smuzhiyun }
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun 
130*4882a593Smuzhiyun /**
131*4882a593Smuzhiyun  * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect CRT presence.
132*4882a593Smuzhiyun  *
133*4882a593Smuzhiyun  * \return true if CRT is connected.
134*4882a593Smuzhiyun  * \return false if CRT is disconnected.
135*4882a593Smuzhiyun  */
cdv_intel_crt_detect_hotplug(struct drm_connector * connector,bool force)136*4882a593Smuzhiyun static bool cdv_intel_crt_detect_hotplug(struct drm_connector *connector,
137*4882a593Smuzhiyun 								bool force)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun 	struct drm_device *dev = connector->dev;
140*4882a593Smuzhiyun 	u32 hotplug_en;
141*4882a593Smuzhiyun 	int i, tries = 0, ret = false;
142*4882a593Smuzhiyun 	u32 orig;
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun 	/*
145*4882a593Smuzhiyun 	 * On a CDV thep, CRT detect sequence need to be done twice
146*4882a593Smuzhiyun 	 * to get a reliable result.
147*4882a593Smuzhiyun 	 */
148*4882a593Smuzhiyun 	tries = 2;
149*4882a593Smuzhiyun 
150*4882a593Smuzhiyun 	orig = hotplug_en = REG_READ(PORT_HOTPLUG_EN);
151*4882a593Smuzhiyun 	hotplug_en &= ~(CRT_HOTPLUG_DETECT_MASK);
152*4882a593Smuzhiyun 	hotplug_en |= CRT_HOTPLUG_FORCE_DETECT;
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun 	hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
155*4882a593Smuzhiyun 	hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun 	for (i = 0; i < tries ; i++) {
158*4882a593Smuzhiyun 		unsigned long timeout;
159*4882a593Smuzhiyun 		/* turn on the FORCE_DETECT */
160*4882a593Smuzhiyun 		REG_WRITE(PORT_HOTPLUG_EN, hotplug_en);
161*4882a593Smuzhiyun 		timeout = jiffies + msecs_to_jiffies(1000);
162*4882a593Smuzhiyun 		/* wait for FORCE_DETECT to go off */
163*4882a593Smuzhiyun 		do {
164*4882a593Smuzhiyun 			if (!(REG_READ(PORT_HOTPLUG_EN) &
165*4882a593Smuzhiyun 					CRT_HOTPLUG_FORCE_DETECT))
166*4882a593Smuzhiyun 				break;
167*4882a593Smuzhiyun 			msleep(1);
168*4882a593Smuzhiyun 		} while (time_after(timeout, jiffies));
169*4882a593Smuzhiyun 	}
170*4882a593Smuzhiyun 
171*4882a593Smuzhiyun 	if ((REG_READ(PORT_HOTPLUG_STAT) & CRT_HOTPLUG_MONITOR_MASK) !=
172*4882a593Smuzhiyun 	    CRT_HOTPLUG_MONITOR_NONE)
173*4882a593Smuzhiyun 		ret = true;
174*4882a593Smuzhiyun 
175*4882a593Smuzhiyun 	 /* clear the interrupt we just generated, if any */
176*4882a593Smuzhiyun 	REG_WRITE(PORT_HOTPLUG_STAT, CRT_HOTPLUG_INT_STATUS);
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun 	/* and put the bits back */
179*4882a593Smuzhiyun 	REG_WRITE(PORT_HOTPLUG_EN, orig);
180*4882a593Smuzhiyun 	return ret;
181*4882a593Smuzhiyun }
182*4882a593Smuzhiyun 
cdv_intel_crt_detect(struct drm_connector * connector,bool force)183*4882a593Smuzhiyun static enum drm_connector_status cdv_intel_crt_detect(
184*4882a593Smuzhiyun 				struct drm_connector *connector, bool force)
185*4882a593Smuzhiyun {
186*4882a593Smuzhiyun 	if (cdv_intel_crt_detect_hotplug(connector, force))
187*4882a593Smuzhiyun 		return connector_status_connected;
188*4882a593Smuzhiyun 	else
189*4882a593Smuzhiyun 		return connector_status_disconnected;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun 
cdv_intel_crt_destroy(struct drm_connector * connector)192*4882a593Smuzhiyun static void cdv_intel_crt_destroy(struct drm_connector *connector)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun 	struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun 	psb_intel_i2c_destroy(gma_encoder->ddc_bus);
197*4882a593Smuzhiyun 	drm_connector_unregister(connector);
198*4882a593Smuzhiyun 	drm_connector_cleanup(connector);
199*4882a593Smuzhiyun 	kfree(connector);
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun 
cdv_intel_crt_get_modes(struct drm_connector * connector)202*4882a593Smuzhiyun static int cdv_intel_crt_get_modes(struct drm_connector *connector)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun 	struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
205*4882a593Smuzhiyun 	return psb_intel_ddc_get_modes(connector,
206*4882a593Smuzhiyun 				       &gma_encoder->ddc_bus->adapter);
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun 
cdv_intel_crt_set_property(struct drm_connector * connector,struct drm_property * property,uint64_t value)209*4882a593Smuzhiyun static int cdv_intel_crt_set_property(struct drm_connector *connector,
210*4882a593Smuzhiyun 				  struct drm_property *property,
211*4882a593Smuzhiyun 				  uint64_t value)
212*4882a593Smuzhiyun {
213*4882a593Smuzhiyun 	return 0;
214*4882a593Smuzhiyun }
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun /*
217*4882a593Smuzhiyun  * Routines for controlling stuff on the analog port
218*4882a593Smuzhiyun  */
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs cdv_intel_crt_helper_funcs = {
221*4882a593Smuzhiyun 	.dpms = cdv_intel_crt_dpms,
222*4882a593Smuzhiyun 	.prepare = gma_encoder_prepare,
223*4882a593Smuzhiyun 	.commit = gma_encoder_commit,
224*4882a593Smuzhiyun 	.mode_set = cdv_intel_crt_mode_set,
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun static const struct drm_connector_funcs cdv_intel_crt_connector_funcs = {
228*4882a593Smuzhiyun 	.dpms = drm_helper_connector_dpms,
229*4882a593Smuzhiyun 	.detect = cdv_intel_crt_detect,
230*4882a593Smuzhiyun 	.fill_modes = drm_helper_probe_single_connector_modes,
231*4882a593Smuzhiyun 	.destroy = cdv_intel_crt_destroy,
232*4882a593Smuzhiyun 	.set_property = cdv_intel_crt_set_property,
233*4882a593Smuzhiyun };
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun static const struct drm_connector_helper_funcs
236*4882a593Smuzhiyun 				cdv_intel_crt_connector_helper_funcs = {
237*4882a593Smuzhiyun 	.mode_valid = cdv_intel_crt_mode_valid,
238*4882a593Smuzhiyun 	.get_modes = cdv_intel_crt_get_modes,
239*4882a593Smuzhiyun 	.best_encoder = gma_best_encoder,
240*4882a593Smuzhiyun };
241*4882a593Smuzhiyun 
cdv_intel_crt_init(struct drm_device * dev,struct psb_intel_mode_device * mode_dev)242*4882a593Smuzhiyun void cdv_intel_crt_init(struct drm_device *dev,
243*4882a593Smuzhiyun 			struct psb_intel_mode_device *mode_dev)
244*4882a593Smuzhiyun {
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	struct gma_connector *gma_connector;
247*4882a593Smuzhiyun 	struct gma_encoder *gma_encoder;
248*4882a593Smuzhiyun 	struct drm_connector *connector;
249*4882a593Smuzhiyun 	struct drm_encoder *encoder;
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	u32 i2c_reg;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	gma_encoder = kzalloc(sizeof(struct gma_encoder), GFP_KERNEL);
254*4882a593Smuzhiyun 	if (!gma_encoder)
255*4882a593Smuzhiyun 		return;
256*4882a593Smuzhiyun 
257*4882a593Smuzhiyun 	gma_connector = kzalloc(sizeof(struct gma_connector), GFP_KERNEL);
258*4882a593Smuzhiyun 	if (!gma_connector)
259*4882a593Smuzhiyun 		goto failed_connector;
260*4882a593Smuzhiyun 
261*4882a593Smuzhiyun 	connector = &gma_connector->base;
262*4882a593Smuzhiyun 	connector->polled = DRM_CONNECTOR_POLL_HPD;
263*4882a593Smuzhiyun 	drm_connector_init(dev, connector,
264*4882a593Smuzhiyun 		&cdv_intel_crt_connector_funcs, DRM_MODE_CONNECTOR_VGA);
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun 	encoder = &gma_encoder->base;
267*4882a593Smuzhiyun 	drm_simple_encoder_init(dev, encoder, DRM_MODE_ENCODER_DAC);
268*4882a593Smuzhiyun 
269*4882a593Smuzhiyun 	gma_connector_attach_encoder(gma_connector, gma_encoder);
270*4882a593Smuzhiyun 
271*4882a593Smuzhiyun 	/* Set up the DDC bus. */
272*4882a593Smuzhiyun 	i2c_reg = GPIOA;
273*4882a593Smuzhiyun 	/* Remove the following code for CDV */
274*4882a593Smuzhiyun 	/*
275*4882a593Smuzhiyun 	if (dev_priv->crt_ddc_bus != 0)
276*4882a593Smuzhiyun 		i2c_reg = dev_priv->crt_ddc_bus;
277*4882a593Smuzhiyun 	}*/
278*4882a593Smuzhiyun 	gma_encoder->ddc_bus = psb_intel_i2c_create(dev,
279*4882a593Smuzhiyun 							  i2c_reg, "CRTDDC_A");
280*4882a593Smuzhiyun 	if (!gma_encoder->ddc_bus) {
281*4882a593Smuzhiyun 		dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
282*4882a593Smuzhiyun 			   "failed.\n");
283*4882a593Smuzhiyun 		goto failed_ddc;
284*4882a593Smuzhiyun 	}
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun 	gma_encoder->type = INTEL_OUTPUT_ANALOG;
287*4882a593Smuzhiyun 	/*
288*4882a593Smuzhiyun 	psb_intel_output->clone_mask = (1 << INTEL_ANALOG_CLONE_BIT);
289*4882a593Smuzhiyun 	psb_intel_output->crtc_mask = (1 << 0) | (1 << 1);
290*4882a593Smuzhiyun 	*/
291*4882a593Smuzhiyun 	connector->interlace_allowed = 0;
292*4882a593Smuzhiyun 	connector->doublescan_allowed = 0;
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun 	drm_encoder_helper_add(encoder, &cdv_intel_crt_helper_funcs);
295*4882a593Smuzhiyun 	drm_connector_helper_add(connector,
296*4882a593Smuzhiyun 					&cdv_intel_crt_connector_helper_funcs);
297*4882a593Smuzhiyun 
298*4882a593Smuzhiyun 	drm_connector_register(connector);
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun 	return;
301*4882a593Smuzhiyun failed_ddc:
302*4882a593Smuzhiyun 	drm_encoder_cleanup(&gma_encoder->base);
303*4882a593Smuzhiyun 	drm_connector_cleanup(&gma_connector->base);
304*4882a593Smuzhiyun 	kfree(gma_connector);
305*4882a593Smuzhiyun failed_connector:
306*4882a593Smuzhiyun 	kfree(gma_encoder);
307*4882a593Smuzhiyun 	return;
308*4882a593Smuzhiyun }
309