1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Cloned from drivers/media/video/s5p-tv/regs-vp.h 5*4882a593Smuzhiyun * 6*4882a593Smuzhiyun * Copyright (c) 2010-2011 Samsung Electronics Co., Ltd. 7*4882a593Smuzhiyun * http://www.samsung.com/ 8*4882a593Smuzhiyun * 9*4882a593Smuzhiyun * Video processor register header file for Samsung Mixer driver 10*4882a593Smuzhiyun */ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun #ifndef SAMSUNG_REGS_VP_H 13*4882a593Smuzhiyun #define SAMSUNG_REGS_VP_H 14*4882a593Smuzhiyun 15*4882a593Smuzhiyun /* 16*4882a593Smuzhiyun * Register part 17*4882a593Smuzhiyun */ 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun #define VP_ENABLE 0x0000 20*4882a593Smuzhiyun #define VP_SRESET 0x0004 21*4882a593Smuzhiyun #define VP_SHADOW_UPDATE 0x0008 22*4882a593Smuzhiyun #define VP_FIELD_ID 0x000C 23*4882a593Smuzhiyun #define VP_MODE 0x0010 24*4882a593Smuzhiyun #define VP_IMG_SIZE_Y 0x0014 25*4882a593Smuzhiyun #define VP_IMG_SIZE_C 0x0018 26*4882a593Smuzhiyun #define VP_PER_RATE_CTRL 0x001C 27*4882a593Smuzhiyun #define VP_TOP_Y_PTR 0x0028 28*4882a593Smuzhiyun #define VP_BOT_Y_PTR 0x002C 29*4882a593Smuzhiyun #define VP_TOP_C_PTR 0x0030 30*4882a593Smuzhiyun #define VP_BOT_C_PTR 0x0034 31*4882a593Smuzhiyun #define VP_ENDIAN_MODE 0x03CC 32*4882a593Smuzhiyun #define VP_SRC_H_POSITION 0x0044 33*4882a593Smuzhiyun #define VP_SRC_V_POSITION 0x0048 34*4882a593Smuzhiyun #define VP_SRC_WIDTH 0x004C 35*4882a593Smuzhiyun #define VP_SRC_HEIGHT 0x0050 36*4882a593Smuzhiyun #define VP_DST_H_POSITION 0x0054 37*4882a593Smuzhiyun #define VP_DST_V_POSITION 0x0058 38*4882a593Smuzhiyun #define VP_DST_WIDTH 0x005C 39*4882a593Smuzhiyun #define VP_DST_HEIGHT 0x0060 40*4882a593Smuzhiyun #define VP_H_RATIO 0x0064 41*4882a593Smuzhiyun #define VP_V_RATIO 0x0068 42*4882a593Smuzhiyun #define VP_POLY8_Y0_LL 0x006C 43*4882a593Smuzhiyun #define VP_POLY4_Y0_LL 0x00EC 44*4882a593Smuzhiyun #define VP_POLY4_C0_LL 0x012C 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun /* 47*4882a593Smuzhiyun * Bit definition part 48*4882a593Smuzhiyun */ 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun /* generates mask for range of bits */ 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun #define VP_MASK(high_bit, low_bit) \ 53*4882a593Smuzhiyun (((2 << ((high_bit) - (low_bit))) - 1) << (low_bit)) 54*4882a593Smuzhiyun 55*4882a593Smuzhiyun #define VP_MASK_VAL(val, high_bit, low_bit) \ 56*4882a593Smuzhiyun (((val) << (low_bit)) & VP_MASK(high_bit, low_bit)) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* VP_ENABLE */ 59*4882a593Smuzhiyun #define VP_ENABLE_ON (1 << 0) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun /* VP_SRESET */ 62*4882a593Smuzhiyun #define VP_SRESET_PROCESSING (1 << 0) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun /* VP_SHADOW_UPDATE */ 65*4882a593Smuzhiyun #define VP_SHADOW_UPDATE_ENABLE (1 << 0) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun /* VP_MODE */ 68*4882a593Smuzhiyun #define VP_MODE_NV12 (0 << 6) 69*4882a593Smuzhiyun #define VP_MODE_NV21 (1 << 6) 70*4882a593Smuzhiyun #define VP_MODE_LINE_SKIP (1 << 5) 71*4882a593Smuzhiyun #define VP_MODE_MEM_LINEAR (0 << 4) 72*4882a593Smuzhiyun #define VP_MODE_MEM_TILED (1 << 4) 73*4882a593Smuzhiyun #define VP_MODE_FMT_MASK (5 << 4) 74*4882a593Smuzhiyun #define VP_MODE_FIELD_ID_AUTO_TOGGLING (1 << 2) 75*4882a593Smuzhiyun #define VP_MODE_2D_IPC (1 << 1) 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun /* VP_IMG_SIZE_Y */ 78*4882a593Smuzhiyun /* VP_IMG_SIZE_C */ 79*4882a593Smuzhiyun #define VP_IMG_HSIZE(x) VP_MASK_VAL(x, 29, 16) 80*4882a593Smuzhiyun #define VP_IMG_VSIZE(x) VP_MASK_VAL(x, 13, 0) 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun /* VP_SRC_H_POSITION */ 83*4882a593Smuzhiyun #define VP_SRC_H_POSITION_VAL(x) VP_MASK_VAL(x, 14, 4) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* VP_ENDIAN_MODE */ 86*4882a593Smuzhiyun #define VP_ENDIAN_MODE_LITTLE (1 << 0) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun #endif /* SAMSUNG_REGS_VP_H */ 89