1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* drivers/gpu/drm/exynos/regs-rotator.h 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Copyright (c) 2012 Samsung Electronics Co., Ltd. 5*4882a593Smuzhiyun * http://www.samsung.com/ 6*4882a593Smuzhiyun * 7*4882a593Smuzhiyun * Register definition file for Samsung Rotator Interface (Rotator) driver 8*4882a593Smuzhiyun */ 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun #ifndef EXYNOS_REGS_ROTATOR_H 11*4882a593Smuzhiyun #define EXYNOS_REGS_ROTATOR_H 12*4882a593Smuzhiyun 13*4882a593Smuzhiyun /* Configuration */ 14*4882a593Smuzhiyun #define ROT_CONFIG 0x00 15*4882a593Smuzhiyun #define ROT_CONFIG_IRQ (3 << 8) 16*4882a593Smuzhiyun 17*4882a593Smuzhiyun /* Image Control */ 18*4882a593Smuzhiyun #define ROT_CONTROL 0x10 19*4882a593Smuzhiyun #define ROT_CONTROL_PATTERN_WRITE (1 << 16) 20*4882a593Smuzhiyun #define ROT_CONTROL_FMT_YCBCR420_2P (1 << 8) 21*4882a593Smuzhiyun #define ROT_CONTROL_FMT_RGB888 (6 << 8) 22*4882a593Smuzhiyun #define ROT_CONTROL_FMT_MASK (7 << 8) 23*4882a593Smuzhiyun #define ROT_CONTROL_FLIP_VERTICAL (2 << 6) 24*4882a593Smuzhiyun #define ROT_CONTROL_FLIP_HORIZONTAL (3 << 6) 25*4882a593Smuzhiyun #define ROT_CONTROL_FLIP_MASK (3 << 6) 26*4882a593Smuzhiyun #define ROT_CONTROL_ROT_90 (1 << 4) 27*4882a593Smuzhiyun #define ROT_CONTROL_ROT_180 (2 << 4) 28*4882a593Smuzhiyun #define ROT_CONTROL_ROT_270 (3 << 4) 29*4882a593Smuzhiyun #define ROT_CONTROL_ROT_MASK (3 << 4) 30*4882a593Smuzhiyun #define ROT_CONTROL_START (1 << 0) 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun /* Status */ 33*4882a593Smuzhiyun #define ROT_STATUS 0x20 34*4882a593Smuzhiyun #define ROT_STATUS_IRQ_PENDING(x) (1 << (x)) 35*4882a593Smuzhiyun #define ROT_STATUS_IRQ(x) (((x) >> 8) & 0x3) 36*4882a593Smuzhiyun #define ROT_STATUS_IRQ_VAL_COMPLETE 1 37*4882a593Smuzhiyun #define ROT_STATUS_IRQ_VAL_ILLEGAL 2 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun /* Buffer Address */ 40*4882a593Smuzhiyun #define ROT_SRC_BUF_ADDR(n) (0x30 + ((n) << 2)) 41*4882a593Smuzhiyun #define ROT_DST_BUF_ADDR(n) (0x50 + ((n) << 2)) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun /* Buffer Size */ 44*4882a593Smuzhiyun #define ROT_SRC_BUF_SIZE 0x3c 45*4882a593Smuzhiyun #define ROT_DST_BUF_SIZE 0x5c 46*4882a593Smuzhiyun #define ROT_SET_BUF_SIZE_H(x) ((x) << 16) 47*4882a593Smuzhiyun #define ROT_SET_BUF_SIZE_W(x) ((x) << 0) 48*4882a593Smuzhiyun #define ROT_GET_BUF_SIZE_H(x) ((x) >> 16) 49*4882a593Smuzhiyun #define ROT_GET_BUF_SIZE_W(x) ((x) & 0xffff) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Crop Position */ 52*4882a593Smuzhiyun #define ROT_SRC_CROP_POS 0x40 53*4882a593Smuzhiyun #define ROT_DST_CROP_POS 0x60 54*4882a593Smuzhiyun #define ROT_CROP_POS_Y(x) ((x) << 16) 55*4882a593Smuzhiyun #define ROT_CROP_POS_X(x) ((x) << 0) 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun /* Source Crop Size */ 58*4882a593Smuzhiyun #define ROT_SRC_CROP_SIZE 0x44 59*4882a593Smuzhiyun #define ROT_SRC_CROP_SIZE_H(x) ((x) << 16) 60*4882a593Smuzhiyun #define ROT_SRC_CROP_SIZE_W(x) ((x) << 0) 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun /* Round to nearest aligned value */ 63*4882a593Smuzhiyun #define ROT_ALIGN(x, align, mask) (((x) + (1 << ((align) - 1))) & (mask)) 64*4882a593Smuzhiyun /* Minimum limit value */ 65*4882a593Smuzhiyun #define ROT_MIN(min, mask) (((min) + ~(mask)) & (mask)) 66*4882a593Smuzhiyun /* Maximum limit value */ 67*4882a593Smuzhiyun #define ROT_MAX(max, mask) ((max) & (mask)) 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #endif /* EXYNOS_REGS_ROTATOR_H */ 70*4882a593Smuzhiyun 71