xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/exynos/regs-decon5433.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (C) 2014 Samsung Electronics Co.Ltd
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #ifndef EXYNOS_REGS_DECON5433_H
7*4882a593Smuzhiyun #define EXYNOS_REGS_DECON5433_H
8*4882a593Smuzhiyun 
9*4882a593Smuzhiyun /* Exynos543X DECON */
10*4882a593Smuzhiyun #define DECON_VIDCON0			0x0000
11*4882a593Smuzhiyun #define DECON_VIDOUTCON0		0x0010
12*4882a593Smuzhiyun #define DECON_WINCONx(n)		(0x0020 + ((n) * 4))
13*4882a593Smuzhiyun #define DECON_VIDOSDxH(n)		(0x0080 + ((n) * 4))
14*4882a593Smuzhiyun #define DECON_SHADOWCON			0x00A0
15*4882a593Smuzhiyun #define DECON_VIDOSDxA(n)		(0x00B0 + ((n) * 0x20))
16*4882a593Smuzhiyun #define DECON_VIDOSDxB(n)		(0x00B4 + ((n) * 0x20))
17*4882a593Smuzhiyun #define DECON_VIDOSDxC(n)		(0x00B8 + ((n) * 0x20))
18*4882a593Smuzhiyun #define DECON_VIDOSDxD(n)		(0x00BC + ((n) * 0x20))
19*4882a593Smuzhiyun #define DECON_VIDOSDxE(n)		(0x00C0 + ((n) * 0x20))
20*4882a593Smuzhiyun #define DECON_VIDW0xADD0B0(n)		(0x0150 + ((n) * 0x10))
21*4882a593Smuzhiyun #define DECON_VIDW0xADD0B1(n)		(0x0154 + ((n) * 0x10))
22*4882a593Smuzhiyun #define DECON_VIDW0xADD0B2(n)		(0x0158 + ((n) * 0x10))
23*4882a593Smuzhiyun #define DECON_VIDW0xADD1B0(n)		(0x01A0 + ((n) * 0x10))
24*4882a593Smuzhiyun #define DECON_VIDW0xADD1B1(n)		(0x01A4 + ((n) * 0x10))
25*4882a593Smuzhiyun #define DECON_VIDW0xADD1B2(n)		(0x01A8 + ((n) * 0x10))
26*4882a593Smuzhiyun #define DECON_VIDW0xADD2(n)		(0x0200 + ((n) * 4))
27*4882a593Smuzhiyun #define DECON_LOCALxSIZE(n)		(0x0214 + ((n) * 4))
28*4882a593Smuzhiyun #define DECON_VIDINTCON0		0x0220
29*4882a593Smuzhiyun #define DECON_VIDINTCON1		0x0224
30*4882a593Smuzhiyun #define DECON_WxKEYCON0(n)		(0x0230 + ((n - 1) * 8))
31*4882a593Smuzhiyun #define DECON_WxKEYCON1(n)		(0x0234 + ((n - 1) * 8))
32*4882a593Smuzhiyun #define DECON_WxKEYALPHA(n)		(0x0250 + ((n - 1) * 4))
33*4882a593Smuzhiyun #define DECON_WINxMAP(n)		(0x0270 + ((n) * 4))
34*4882a593Smuzhiyun #define DECON_QOSLUT07_00		0x02C0
35*4882a593Smuzhiyun #define DECON_QOSLUT15_08		0x02C4
36*4882a593Smuzhiyun #define DECON_QOSCTRL			0x02C8
37*4882a593Smuzhiyun #define DECON_BLENDERQx(n)		(0x0300 + ((n - 1) * 4))
38*4882a593Smuzhiyun #define DECON_BLENDCON			0x0310
39*4882a593Smuzhiyun #define DECON_OPE_VIDW0xADD0(n)		(0x0400 + ((n) * 4))
40*4882a593Smuzhiyun #define DECON_OPE_VIDW0xADD1(n)		(0x0414 + ((n) * 4))
41*4882a593Smuzhiyun #define DECON_FRAMEFIFO_REG7		0x051C
42*4882a593Smuzhiyun #define DECON_FRAMEFIFO_REG8		0x0520
43*4882a593Smuzhiyun #define DECON_FRAMEFIFO_STATUS		0x0524
44*4882a593Smuzhiyun #define DECON_CMU			0x1404
45*4882a593Smuzhiyun #define DECON_UPDATE			0x1410
46*4882a593Smuzhiyun #define DECON_CRFMID			0x1414
47*4882a593Smuzhiyun #define DECON_UPDATE_SCHEME		0x1438
48*4882a593Smuzhiyun #define DECON_VIDCON1			0x2000
49*4882a593Smuzhiyun #define DECON_VIDCON2			0x2004
50*4882a593Smuzhiyun #define DECON_VIDCON3			0x2008
51*4882a593Smuzhiyun #define DECON_VIDCON4			0x200C
52*4882a593Smuzhiyun #define DECON_VIDTCON2			0x2028
53*4882a593Smuzhiyun #define DECON_FRAME_SIZE		0x2038
54*4882a593Smuzhiyun #define DECON_LINECNT_OP_THRESHOLD	0x203C
55*4882a593Smuzhiyun #define DECON_TRIGCON			0x2040
56*4882a593Smuzhiyun #define DECON_TRIGSKIP			0x2050
57*4882a593Smuzhiyun #define DECON_CRCRDATA			0x20B0
58*4882a593Smuzhiyun #define DECON_CRCCTRL			0x20B4
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun /* Exynos5430 DECON */
61*4882a593Smuzhiyun #define DECON_VIDTCON0			0x2020
62*4882a593Smuzhiyun #define DECON_VIDTCON1			0x2024
63*4882a593Smuzhiyun 
64*4882a593Smuzhiyun /* Exynos5433 DECON */
65*4882a593Smuzhiyun #define DECON_VIDTCON00			0x2010
66*4882a593Smuzhiyun #define DECON_VIDTCON01			0x2014
67*4882a593Smuzhiyun #define DECON_VIDTCON10			0x2018
68*4882a593Smuzhiyun #define DECON_VIDTCON11			0x201C
69*4882a593Smuzhiyun 
70*4882a593Smuzhiyun /* Exynos543X DECON Internal */
71*4882a593Smuzhiyun #define DECON_W013DSTREOCON		0x0320
72*4882a593Smuzhiyun #define DECON_W233DSTREOCON		0x0324
73*4882a593Smuzhiyun #define DECON_FRAMEFIFO_REG0		0x0500
74*4882a593Smuzhiyun #define DECON_ENHANCER_CTRL		0x2100
75*4882a593Smuzhiyun 
76*4882a593Smuzhiyun /* Exynos543X DECON TV */
77*4882a593Smuzhiyun #define DECON_VCLKCON0			0x0014
78*4882a593Smuzhiyun #define DECON_VIDINTCON2		0x0228
79*4882a593Smuzhiyun #define DECON_VIDINTCON3		0x022C
80*4882a593Smuzhiyun 
81*4882a593Smuzhiyun /* VIDCON0 */
82*4882a593Smuzhiyun #define VIDCON0_SWRESET			(1 << 28)
83*4882a593Smuzhiyun #define VIDCON0_CLKVALUP		(1 << 14)
84*4882a593Smuzhiyun #define VIDCON0_VLCKFREE		(1 << 5)
85*4882a593Smuzhiyun #define VIDCON0_STOP_STATUS		(1 << 2)
86*4882a593Smuzhiyun #define VIDCON0_ENVID			(1 << 1)
87*4882a593Smuzhiyun #define VIDCON0_ENVID_F			(1 << 0)
88*4882a593Smuzhiyun 
89*4882a593Smuzhiyun /* VIDOUTCON0 */
90*4882a593Smuzhiyun #define VIDOUT_INTERLACE_FIELD_F	(1 << 29)
91*4882a593Smuzhiyun #define VIDOUT_INTERLACE_EN_F		(1 << 28)
92*4882a593Smuzhiyun #define VIDOUT_LCD_ON			(1 << 24)
93*4882a593Smuzhiyun #define VIDOUT_IF_F_MASK		(0x3 << 20)
94*4882a593Smuzhiyun #define VIDOUT_RGB_IF			(0x0 << 20)
95*4882a593Smuzhiyun #define VIDOUT_COMMAND_IF		(0x2 << 20)
96*4882a593Smuzhiyun 
97*4882a593Smuzhiyun /* WINCONx */
98*4882a593Smuzhiyun #define WINCONx_HAWSWP_F		(1 << 16)
99*4882a593Smuzhiyun #define WINCONx_WSWP_F			(1 << 15)
100*4882a593Smuzhiyun #define WINCONx_BURSTLEN_MASK		(0x3 << 10)
101*4882a593Smuzhiyun #define WINCONx_BURSTLEN_16WORD		(0x0 << 10)
102*4882a593Smuzhiyun #define WINCONx_BURSTLEN_8WORD		(0x1 << 10)
103*4882a593Smuzhiyun #define WINCONx_BURSTLEN_4WORD		(0x2 << 10)
104*4882a593Smuzhiyun #define WINCONx_ALPHA_MUL_F		(1 << 7)
105*4882a593Smuzhiyun #define WINCONx_BLD_PIX_F		(1 << 6)
106*4882a593Smuzhiyun #define WINCONx_BPPMODE_MASK		(0xf << 2)
107*4882a593Smuzhiyun #define WINCONx_BPPMODE_16BPP_565	(0x5 << 2)
108*4882a593Smuzhiyun #define WINCONx_BPPMODE_16BPP_A1555	(0x6 << 2)
109*4882a593Smuzhiyun #define WINCONx_BPPMODE_16BPP_I1555	(0x7 << 2)
110*4882a593Smuzhiyun #define WINCONx_BPPMODE_24BPP_888	(0xb << 2)
111*4882a593Smuzhiyun #define WINCONx_BPPMODE_24BPP_A1887	(0xc << 2)
112*4882a593Smuzhiyun #define WINCONx_BPPMODE_25BPP_A1888	(0xd << 2)
113*4882a593Smuzhiyun #define WINCONx_BPPMODE_32BPP_A8888	(0xd << 2)
114*4882a593Smuzhiyun #define WINCONx_BPPMODE_16BPP_A4444	(0xe << 2)
115*4882a593Smuzhiyun #define WINCONx_ALPHA_SEL_F		(1 << 1)
116*4882a593Smuzhiyun #define WINCONx_ENWIN_F			(1 << 0)
117*4882a593Smuzhiyun #define WINCONx_BLEND_MODE_MASK		(0xc2)
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun /* SHADOWCON */
120*4882a593Smuzhiyun #define SHADOWCON_PROTECT_MASK		GENMASK(14, 10)
121*4882a593Smuzhiyun #define SHADOWCON_Wx_PROTECT(n)		(1 << (10 + (n)))
122*4882a593Smuzhiyun 
123*4882a593Smuzhiyun /* VIDOSDxC */
124*4882a593Smuzhiyun #define VIDOSDxC_ALPHA0_RGB_MASK	(0xffffff)
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun /* VIDOSDxD */
127*4882a593Smuzhiyun #define VIDOSD_Wx_ALPHA_R_F(n)		(((n) & 0xff) << 16)
128*4882a593Smuzhiyun #define VIDOSD_Wx_ALPHA_G_F(n)		(((n) & 0xff) << 8)
129*4882a593Smuzhiyun #define VIDOSD_Wx_ALPHA_B_F(n)		(((n) & 0xff) << 0)
130*4882a593Smuzhiyun 
131*4882a593Smuzhiyun /* VIDINTCON0 */
132*4882a593Smuzhiyun #define VIDINTCON0_FRAMEDONE		(1 << 17)
133*4882a593Smuzhiyun #define VIDINTCON0_FRAMESEL_BP		(0 << 15)
134*4882a593Smuzhiyun #define VIDINTCON0_FRAMESEL_VS		(1 << 15)
135*4882a593Smuzhiyun #define VIDINTCON0_FRAMESEL_AC		(2 << 15)
136*4882a593Smuzhiyun #define VIDINTCON0_FRAMESEL_FP		(3 << 15)
137*4882a593Smuzhiyun #define VIDINTCON0_INTFRMEN		(1 << 12)
138*4882a593Smuzhiyun #define VIDINTCON0_INTEN		(1 << 0)
139*4882a593Smuzhiyun 
140*4882a593Smuzhiyun /* VIDINTCON1 */
141*4882a593Smuzhiyun #define VIDINTCON1_INTFRMDONEPEND	(1 << 2)
142*4882a593Smuzhiyun #define VIDINTCON1_INTFRMPEND		(1 << 1)
143*4882a593Smuzhiyun #define VIDINTCON1_INTFIFOPEND		(1 << 0)
144*4882a593Smuzhiyun 
145*4882a593Smuzhiyun /* DECON_CMU */
146*4882a593Smuzhiyun #define CMU_CLKGAGE_MODE_SFR_F		(1 << 1)
147*4882a593Smuzhiyun #define CMU_CLKGAGE_MODE_MEM_F		(1 << 0)
148*4882a593Smuzhiyun 
149*4882a593Smuzhiyun /* DECON_UPDATE */
150*4882a593Smuzhiyun #define STANDALONE_UPDATE_F		(1 << 0)
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun /* DECON_VIDCON1 */
153*4882a593Smuzhiyun #define VIDCON1_LINECNT_MASK		(0x0fff << 16)
154*4882a593Smuzhiyun #define VIDCON1_I80_ACTIVE		(1 << 15)
155*4882a593Smuzhiyun #define VIDCON1_VSTATUS_MASK		(0x3 << 13)
156*4882a593Smuzhiyun #define VIDCON1_VSTATUS_VS		(0 << 13)
157*4882a593Smuzhiyun #define VIDCON1_VSTATUS_BP		(1 << 13)
158*4882a593Smuzhiyun #define VIDCON1_VSTATUS_AC		(2 << 13)
159*4882a593Smuzhiyun #define VIDCON1_VSTATUS_FP		(3 << 13)
160*4882a593Smuzhiyun #define VIDCON1_VCLK_MASK		(0x3 << 9)
161*4882a593Smuzhiyun #define VIDCON1_VCLK_RUN_VDEN_DISABLE	(0x3 << 9)
162*4882a593Smuzhiyun #define VIDCON1_VCLK_HOLD		(0x0 << 9)
163*4882a593Smuzhiyun #define VIDCON1_VCLK_RUN		(0x1 << 9)
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun /* DECON_VIDTCON00 */
167*4882a593Smuzhiyun #define VIDTCON00_VBPD_F(x)		(((x) & 0xfff) << 16)
168*4882a593Smuzhiyun #define VIDTCON00_VFPD_F(x)		((x) & 0xfff)
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun /* DECON_VIDTCON01 */
171*4882a593Smuzhiyun #define VIDTCON01_VSPW_F(x)		(((x) & 0xfff) << 16)
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /* DECON_VIDTCON10 */
174*4882a593Smuzhiyun #define VIDTCON10_HBPD_F(x)		(((x) & 0xfff) << 16)
175*4882a593Smuzhiyun #define VIDTCON10_HFPD_F(x)		((x) & 0xfff)
176*4882a593Smuzhiyun 
177*4882a593Smuzhiyun /* DECON_VIDTCON11 */
178*4882a593Smuzhiyun #define VIDTCON11_HSPW_F(x)		(((x) & 0xfff) << 16)
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun /* DECON_VIDTCON2 */
181*4882a593Smuzhiyun #define VIDTCON2_LINEVAL(x)		(((x) & 0xfff) << 16)
182*4882a593Smuzhiyun #define VIDTCON2_HOZVAL(x)		((x) & 0xfff)
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun /* TRIGCON */
185*4882a593Smuzhiyun #define TRIGCON_TRIGEN_PER_F		(1 << 31)
186*4882a593Smuzhiyun #define TRIGCON_TRIGEN_F		(1 << 30)
187*4882a593Smuzhiyun #define TRIGCON_TE_AUTO_MASK		(1 << 29)
188*4882a593Smuzhiyun #define TRIGCON_WB_SWTRIGCMD		(1 << 28)
189*4882a593Smuzhiyun #define TRIGCON_SWTRIGCMD_W4BUF		(1 << 26)
190*4882a593Smuzhiyun #define TRIGCON_TRIGMODE_W4BUF		(1 << 25)
191*4882a593Smuzhiyun #define TRIGCON_SWTRIGCMD_W3BUF		(1 << 21)
192*4882a593Smuzhiyun #define TRIGCON_TRIGMODE_W3BUF		(1 << 20)
193*4882a593Smuzhiyun #define TRIGCON_SWTRIGCMD_W2BUF		(1 << 16)
194*4882a593Smuzhiyun #define TRIGCON_TRIGMODE_W2BUF		(1 << 15)
195*4882a593Smuzhiyun #define TRIGCON_SWTRIGCMD_W1BUF		(1 << 11)
196*4882a593Smuzhiyun #define TRIGCON_TRIGMODE_W1BUF		(1 << 10)
197*4882a593Smuzhiyun #define TRIGCON_SWTRIGCMD_W0BUF		(1 << 6)
198*4882a593Smuzhiyun #define TRIGCON_TRIGMODE_W0BUF		(1 << 5)
199*4882a593Smuzhiyun #define TRIGCON_HWTRIGMASK		(1 << 4)
200*4882a593Smuzhiyun #define TRIGCON_HWTRIGEN		(1 << 3)
201*4882a593Smuzhiyun #define TRIGCON_HWTRIG_INV		(1 << 2)
202*4882a593Smuzhiyun #define TRIGCON_SWTRIGCMD		(1 << 1)
203*4882a593Smuzhiyun #define TRIGCON_SWTRIGEN		(1 << 0)
204*4882a593Smuzhiyun 
205*4882a593Smuzhiyun /* DECON_CRCCTRL */
206*4882a593Smuzhiyun #define CRCCTRL_CRCCLKEN		(0x1 << 2)
207*4882a593Smuzhiyun #define CRCCTRL_CRCSTART_F		(0x1 << 1)
208*4882a593Smuzhiyun #define CRCCTRL_CRCEN			(0x1 << 0)
209*4882a593Smuzhiyun #define CRCCTRL_MASK			(0x7)
210*4882a593Smuzhiyun 
211*4882a593Smuzhiyun /* BLENDCON */
212*4882a593Smuzhiyun #define BLEND_NEW			(1 << 0)
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun /* BLENDERQx */
215*4882a593Smuzhiyun #define BLENDERQ_ZERO			0x0
216*4882a593Smuzhiyun #define BLENDERQ_ONE			0x1
217*4882a593Smuzhiyun #define BLENDERQ_ALPHA_A		0x2
218*4882a593Smuzhiyun #define BLENDERQ_ONE_MINUS_ALPHA_A	0x3
219*4882a593Smuzhiyun #define BLENDERQ_ALPHA0			0x6
220*4882a593Smuzhiyun #define BLENDERQ_Q_FUNC_F(n)		(n << 18)
221*4882a593Smuzhiyun #define BLENDERQ_P_FUNC_F(n)		(n << 12)
222*4882a593Smuzhiyun #define BLENDERQ_B_FUNC_F(n)		(n << 6)
223*4882a593Smuzhiyun #define BLENDERQ_A_FUNC_F(n)		(n << 0)
224*4882a593Smuzhiyun 
225*4882a593Smuzhiyun /* BLENDCON */
226*4882a593Smuzhiyun #define BLEND_NEW			(1 << 0)
227*4882a593Smuzhiyun 
228*4882a593Smuzhiyun #endif /* EXYNOS_REGS_DECON5433_H */
229