xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/etnaviv/state.xml.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun #ifndef STATE_XML
2*4882a593Smuzhiyun #define STATE_XML
3*4882a593Smuzhiyun 
4*4882a593Smuzhiyun /* Autogenerated file, DO NOT EDIT manually!
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun This file was generated by the rules-ng-ng headergen tool in this git repository:
7*4882a593Smuzhiyun http://0x04.net/cgit/index.cgi/rules-ng-ng
8*4882a593Smuzhiyun git clone git://0x04.net/rules-ng-ng
9*4882a593Smuzhiyun 
10*4882a593Smuzhiyun The rules-ng-ng source files this header was generated from are:
11*4882a593Smuzhiyun - state.xml     (  26087 bytes, from 2017-12-18 16:51:59)
12*4882a593Smuzhiyun - common.xml    (  35468 bytes, from 2018-01-22 13:48:54)
13*4882a593Smuzhiyun - common_3d.xml (  14615 bytes, from 2017-12-18 16:51:59)
14*4882a593Smuzhiyun - state_hi.xml  (  30232 bytes, from 2018-02-15 15:48:01)
15*4882a593Smuzhiyun - copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
16*4882a593Smuzhiyun - state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)
17*4882a593Smuzhiyun - state_3d.xml  (  79992 bytes, from 2017-12-18 16:51:59)
18*4882a593Smuzhiyun - state_blt.xml (  13405 bytes, from 2017-12-18 16:51:59)
19*4882a593Smuzhiyun - state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)
20*4882a593Smuzhiyun 
21*4882a593Smuzhiyun Copyright (C) 2012-2017 by the following authors:
22*4882a593Smuzhiyun - Wladimir J. van der Laan <laanwj@gmail.com>
23*4882a593Smuzhiyun - Christian Gmeiner <christian.gmeiner@gmail.com>
24*4882a593Smuzhiyun - Lucas Stach <l.stach@pengutronix.de>
25*4882a593Smuzhiyun - Russell King <rmk@arm.linux.org.uk>
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun Permission is hereby granted, free of charge, to any person obtaining a
28*4882a593Smuzhiyun copy of this software and associated documentation files (the "Software"),
29*4882a593Smuzhiyun to deal in the Software without restriction, including without limitation
30*4882a593Smuzhiyun the rights to use, copy, modify, merge, publish, distribute, sub license,
31*4882a593Smuzhiyun and/or sell copies of the Software, and to permit persons to whom the
32*4882a593Smuzhiyun Software is furnished to do so, subject to the following conditions:
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun The above copyright notice and this permission notice (including the
35*4882a593Smuzhiyun next paragraph) shall be included in all copies or substantial portions
36*4882a593Smuzhiyun of the Software.
37*4882a593Smuzhiyun 
38*4882a593Smuzhiyun THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
39*4882a593Smuzhiyun IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
40*4882a593Smuzhiyun FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
41*4882a593Smuzhiyun THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
42*4882a593Smuzhiyun LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
43*4882a593Smuzhiyun FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
44*4882a593Smuzhiyun DEALINGS IN THE SOFTWARE.
45*4882a593Smuzhiyun */
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun 
48*4882a593Smuzhiyun #define VARYING_COMPONENT_USE_UNUSED				0x00000000
49*4882a593Smuzhiyun #define VARYING_COMPONENT_USE_USED				0x00000001
50*4882a593Smuzhiyun #define VARYING_COMPONENT_USE_POINTCOORD_X			0x00000002
51*4882a593Smuzhiyun #define VARYING_COMPONENT_USE_POINTCOORD_Y			0x00000003
52*4882a593Smuzhiyun #define FE_DATA_TYPE_BYTE					0x00000000
53*4882a593Smuzhiyun #define FE_DATA_TYPE_UNSIGNED_BYTE				0x00000001
54*4882a593Smuzhiyun #define FE_DATA_TYPE_SHORT					0x00000002
55*4882a593Smuzhiyun #define FE_DATA_TYPE_UNSIGNED_SHORT				0x00000003
56*4882a593Smuzhiyun #define FE_DATA_TYPE_INT					0x00000004
57*4882a593Smuzhiyun #define FE_DATA_TYPE_UNSIGNED_INT				0x00000005
58*4882a593Smuzhiyun #define FE_DATA_TYPE_FLOAT					0x00000008
59*4882a593Smuzhiyun #define FE_DATA_TYPE_HALF_FLOAT					0x00000009
60*4882a593Smuzhiyun #define FE_DATA_TYPE_FIXED					0x0000000b
61*4882a593Smuzhiyun #define FE_DATA_TYPE_INT_10_10_10_2				0x0000000c
62*4882a593Smuzhiyun #define FE_DATA_TYPE_UNSIGNED_INT_10_10_10_2			0x0000000d
63*4882a593Smuzhiyun #define FE_DATA_TYPE_BYTE_I					0x0000000e
64*4882a593Smuzhiyun #define FE_DATA_TYPE_SHORT_I					0x0000000f
65*4882a593Smuzhiyun #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK		0x000000ff
66*4882a593Smuzhiyun #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT		0
67*4882a593Smuzhiyun #define FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE(x)		(((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_STRIDE__MASK)
68*4882a593Smuzhiyun #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK		0x00ff0000
69*4882a593Smuzhiyun #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT		16
70*4882a593Smuzhiyun #define FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR(x)		(((x) << FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__SHIFT) & FE_VERTEX_STREAM_CONTROL_VERTEX_DIVISOR__MASK)
71*4882a593Smuzhiyun #define VIVS_FE							0x00000000
72*4882a593Smuzhiyun 
73*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG(i0)		       (0x00000600 + 0x4*(i0))
74*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG__ESIZE			0x00000004
75*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG__LEN			0x00000010
76*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK		0x0000000f
77*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT		0
78*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_TYPE__MASK)
79*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK		0x00000030
80*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT		4
81*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_ENDIAN__MASK)
82*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NONCONSECUTIVE		0x00000080
83*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK		0x00000700
84*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT		8
85*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_STREAM__MASK)
86*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK			0x00003000
87*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT		12
88*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_NUM__MASK)
89*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__MASK		0x0000c000
90*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE__SHIFT		14
91*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_OFF		0x00000000
92*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_NORMALIZE_ON		0x00008000
93*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK		0x00ff0000
94*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT		16
95*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_START(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_START__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_START__MASK)
96*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK			0xff000000
97*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT		24
98*4882a593Smuzhiyun #define VIVS_FE_VERTEX_ELEMENT_CONFIG_END(x)			(((x) << VIVS_FE_VERTEX_ELEMENT_CONFIG_END__SHIFT) & VIVS_FE_VERTEX_ELEMENT_CONFIG_END__MASK)
99*4882a593Smuzhiyun 
100*4882a593Smuzhiyun #define VIVS_FE_CMD_STREAM_BASE_ADDR				0x00000640
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun #define VIVS_FE_INDEX_STREAM_BASE_ADDR				0x00000644
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun #define VIVS_FE_INDEX_STREAM_CONTROL				0x00000648
105*4882a593Smuzhiyun #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__MASK			0x00000003
106*4882a593Smuzhiyun #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE__SHIFT		0
107*4882a593Smuzhiyun #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_CHAR		0x00000000
108*4882a593Smuzhiyun #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_SHORT	0x00000001
109*4882a593Smuzhiyun #define VIVS_FE_INDEX_STREAM_CONTROL_TYPE_UNSIGNED_INT		0x00000002
110*4882a593Smuzhiyun #define VIVS_FE_INDEX_STREAM_CONTROL_PRIMITIVE_RESTART		0x00000100
111*4882a593Smuzhiyun 
112*4882a593Smuzhiyun #define VIVS_FE_VERTEX_STREAM_BASE_ADDR				0x0000064c
113*4882a593Smuzhiyun 
114*4882a593Smuzhiyun #define VIVS_FE_VERTEX_STREAM_CONTROL				0x00000650
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun #define VIVS_FE_COMMAND_ADDRESS					0x00000654
117*4882a593Smuzhiyun 
118*4882a593Smuzhiyun #define VIVS_FE_COMMAND_CONTROL					0x00000658
119*4882a593Smuzhiyun #define VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK			0x0000ffff
120*4882a593Smuzhiyun #define VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT			0
121*4882a593Smuzhiyun #define VIVS_FE_COMMAND_CONTROL_PREFETCH(x)			(((x) << VIVS_FE_COMMAND_CONTROL_PREFETCH__SHIFT) & VIVS_FE_COMMAND_CONTROL_PREFETCH__MASK)
122*4882a593Smuzhiyun #define VIVS_FE_COMMAND_CONTROL_ENABLE				0x00010000
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun #define VIVS_FE_DMA_STATUS					0x0000065c
125*4882a593Smuzhiyun 
126*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE					0x00000660
127*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__MASK			0x0000001f
128*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE__SHIFT		0
129*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_IDLE			0x00000000
130*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DEC			0x00000001
131*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR0			0x00000002
132*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD0			0x00000003
133*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_ADR1			0x00000004
134*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LOAD1			0x00000005
135*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DADR			0x00000006
136*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCMD			0x00000007
137*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DCNTL		0x00000008
138*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_3DIDXCNTL		0x00000009
139*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_INITREQDMA		0x0000000a
140*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAWIDX		0x0000000b
141*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_DRAW			0x0000000c
142*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT0		0x0000000d
143*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DRECT1		0x0000000e
144*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA0		0x0000000f
145*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_2DDATA1		0x00000010
146*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAITFIFO		0x00000011
147*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_WAIT			0x00000012
148*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_LINK			0x00000013
149*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_END			0x00000014
150*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_STATE_STALL			0x00000015
151*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__MASK		0x00000300
152*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE__SHIFT		8
153*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_IDLE		0x00000000
154*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_START		0x00000100
155*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_REQ		0x00000200
156*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_DMA_STATE_END		0x00000300
157*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__MASK		0x00000c00
158*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE__SHIFT		10
159*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_IDLE		0x00000000
160*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_RAMVALID	0x00000400
161*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CMD_FETCH_STATE_VALID		0x00000800
162*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__MASK		0x00003000
163*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE__SHIFT		12
164*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_IDLE		0x00000000
165*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_WAITIDX		0x00001000
166*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_REQ_DMA_STATE_CAL		0x00002000
167*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__MASK			0x0000c000
168*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE__SHIFT		14
169*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDLE			0x00000000
170*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_LDADR			0x00004000
171*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_CAL_STATE_IDXCALC		0x00008000
172*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__MASK		0x00030000
173*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE__SHIFT		16
174*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_IDLE		0x00000000
175*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_CKCACHE		0x00010000
176*4882a593Smuzhiyun #define VIVS_FE_DMA_DEBUG_STATE_VE_REQ_STATE_MISS		0x00020000
177*4882a593Smuzhiyun 
178*4882a593Smuzhiyun #define VIVS_FE_DMA_ADDRESS					0x00000664
179*4882a593Smuzhiyun 
180*4882a593Smuzhiyun #define VIVS_FE_DMA_LOW						0x00000668
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun #define VIVS_FE_DMA_HIGH					0x0000066c
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun #define VIVS_FE_AUTO_FLUSH					0x00000670
185*4882a593Smuzhiyun 
186*4882a593Smuzhiyun #define VIVS_FE_PRIMITIVE_RESTART_INDEX				0x00000674
187*4882a593Smuzhiyun 
188*4882a593Smuzhiyun #define VIVS_FE_UNK00678					0x00000678
189*4882a593Smuzhiyun 
190*4882a593Smuzhiyun #define VIVS_FE_UNK0067C					0x0000067c
191*4882a593Smuzhiyun 
192*4882a593Smuzhiyun #define VIVS_FE_VERTEX_STREAMS(i0)			       (0x00000000 + 0x4*(i0))
193*4882a593Smuzhiyun #define VIVS_FE_VERTEX_STREAMS__ESIZE				0x00000004
194*4882a593Smuzhiyun #define VIVS_FE_VERTEX_STREAMS__LEN				0x00000008
195*4882a593Smuzhiyun 
196*4882a593Smuzhiyun #define VIVS_FE_VERTEX_STREAMS_BASE_ADDR(i0)		       (0x00000680 + 0x4*(i0))
197*4882a593Smuzhiyun 
198*4882a593Smuzhiyun #define VIVS_FE_VERTEX_STREAMS_CONTROL(i0)		       (0x000006a0 + 0x4*(i0))
199*4882a593Smuzhiyun 
200*4882a593Smuzhiyun #define VIVS_FE_GENERIC_ATTRIB(i0)			       (0x00000000 + 0x4*(i0))
201*4882a593Smuzhiyun #define VIVS_FE_GENERIC_ATTRIB__ESIZE				0x00000004
202*4882a593Smuzhiyun #define VIVS_FE_GENERIC_ATTRIB__LEN				0x00000010
203*4882a593Smuzhiyun 
204*4882a593Smuzhiyun #define VIVS_FE_GENERIC_ATTRIB_UNK006C0(i0)		       (0x000006c0 + 0x4*(i0))
205*4882a593Smuzhiyun 
206*4882a593Smuzhiyun #define VIVS_FE_GENERIC_ATTRIB_UNK00700(i0)		       (0x00000700 + 0x4*(i0))
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun #define VIVS_FE_GENERIC_ATTRIB_UNK00740(i0)		       (0x00000740 + 0x4*(i0))
209*4882a593Smuzhiyun 
210*4882a593Smuzhiyun #define VIVS_FE_GENERIC_ATTRIB_SCALE(i0)		       (0x00000780 + 0x4*(i0))
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun #define VIVS_FE_HALTI5_UNK007C4					0x000007c4
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun #define VIVS_FE_HALTI5_UNK007D0(i0)			       (0x000007d0 + 0x4*(i0))
215*4882a593Smuzhiyun #define VIVS_FE_HALTI5_UNK007D0__ESIZE				0x00000004
216*4882a593Smuzhiyun #define VIVS_FE_HALTI5_UNK007D0__LEN				0x00000002
217*4882a593Smuzhiyun 
218*4882a593Smuzhiyun #define VIVS_FE_HALTI5_UNK007D8					0x000007d8
219*4882a593Smuzhiyun 
220*4882a593Smuzhiyun #define VIVS_FE_DESC_START					0x000007dc
221*4882a593Smuzhiyun 
222*4882a593Smuzhiyun #define VIVS_FE_DESC_END					0x000007e0
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun #define VIVS_FE_DESC_AVAIL					0x000007e4
225*4882a593Smuzhiyun #define VIVS_FE_DESC_AVAIL_COUNT__MASK				0x0000007f
226*4882a593Smuzhiyun #define VIVS_FE_DESC_AVAIL_COUNT__SHIFT				0
227*4882a593Smuzhiyun #define VIVS_FE_DESC_AVAIL_COUNT(x)				(((x) << VIVS_FE_DESC_AVAIL_COUNT__SHIFT) & VIVS_FE_DESC_AVAIL_COUNT__MASK)
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun #define VIVS_FE_FENCE_WAIT_DATA_LOW				0x000007e8
230*4882a593Smuzhiyun 
231*4882a593Smuzhiyun #define VIVS_FE_FENCE_WAIT_DATA_HIGH				0x000007f4
232*4882a593Smuzhiyun 
233*4882a593Smuzhiyun #define VIVS_FE_ROBUSTNESS_UNK007F8				0x000007f8
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun #define VIVS_GL							0x00000000
236*4882a593Smuzhiyun 
237*4882a593Smuzhiyun #define VIVS_GL_PIPE_SELECT					0x00003800
238*4882a593Smuzhiyun #define VIVS_GL_PIPE_SELECT_PIPE__MASK				0x00000001
239*4882a593Smuzhiyun #define VIVS_GL_PIPE_SELECT_PIPE__SHIFT				0
240*4882a593Smuzhiyun #define VIVS_GL_PIPE_SELECT_PIPE(x)				(((x) << VIVS_GL_PIPE_SELECT_PIPE__SHIFT) & VIVS_GL_PIPE_SELECT_PIPE__MASK)
241*4882a593Smuzhiyun 
242*4882a593Smuzhiyun #define VIVS_GL_EVENT						0x00003804
243*4882a593Smuzhiyun #define VIVS_GL_EVENT_EVENT_ID__MASK				0x0000001f
244*4882a593Smuzhiyun #define VIVS_GL_EVENT_EVENT_ID__SHIFT				0
245*4882a593Smuzhiyun #define VIVS_GL_EVENT_EVENT_ID(x)				(((x) << VIVS_GL_EVENT_EVENT_ID__SHIFT) & VIVS_GL_EVENT_EVENT_ID__MASK)
246*4882a593Smuzhiyun #define VIVS_GL_EVENT_FROM_FE					0x00000020
247*4882a593Smuzhiyun #define VIVS_GL_EVENT_FROM_PE					0x00000040
248*4882a593Smuzhiyun #define VIVS_GL_EVENT_FROM_BLT					0x00000080
249*4882a593Smuzhiyun #define VIVS_GL_EVENT_SOURCE__MASK				0x00001f00
250*4882a593Smuzhiyun #define VIVS_GL_EVENT_SOURCE__SHIFT				8
251*4882a593Smuzhiyun #define VIVS_GL_EVENT_SOURCE(x)					(((x) << VIVS_GL_EVENT_SOURCE__SHIFT) & VIVS_GL_EVENT_SOURCE__MASK)
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun #define VIVS_GL_SEMAPHORE_TOKEN					0x00003808
254*4882a593Smuzhiyun #define VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK			0x0000001f
255*4882a593Smuzhiyun #define VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT			0
256*4882a593Smuzhiyun #define VIVS_GL_SEMAPHORE_TOKEN_FROM(x)				(((x) << VIVS_GL_SEMAPHORE_TOKEN_FROM__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_FROM__MASK)
257*4882a593Smuzhiyun #define VIVS_GL_SEMAPHORE_TOKEN_TO__MASK			0x00001f00
258*4882a593Smuzhiyun #define VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT			8
259*4882a593Smuzhiyun #define VIVS_GL_SEMAPHORE_TOKEN_TO(x)				(((x) << VIVS_GL_SEMAPHORE_TOKEN_TO__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_TO__MASK)
260*4882a593Smuzhiyun #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK			0x30000000
261*4882a593Smuzhiyun #define VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT			28
262*4882a593Smuzhiyun #define VIVS_GL_SEMAPHORE_TOKEN_UNK28(x)			(((x) << VIVS_GL_SEMAPHORE_TOKEN_UNK28__SHIFT) & VIVS_GL_SEMAPHORE_TOKEN_UNK28__MASK)
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun #define VIVS_GL_FLUSH_CACHE					0x0000380c
265*4882a593Smuzhiyun #define VIVS_GL_FLUSH_CACHE_DEPTH				0x00000001
266*4882a593Smuzhiyun #define VIVS_GL_FLUSH_CACHE_COLOR				0x00000002
267*4882a593Smuzhiyun #define VIVS_GL_FLUSH_CACHE_TEXTURE				0x00000004
268*4882a593Smuzhiyun #define VIVS_GL_FLUSH_CACHE_PE2D				0x00000008
269*4882a593Smuzhiyun #define VIVS_GL_FLUSH_CACHE_TEXTUREVS				0x00000010
270*4882a593Smuzhiyun #define VIVS_GL_FLUSH_CACHE_SHADER_L1				0x00000020
271*4882a593Smuzhiyun #define VIVS_GL_FLUSH_CACHE_SHADER_L2				0x00000040
272*4882a593Smuzhiyun #define VIVS_GL_FLUSH_CACHE_UNK10				0x00000400
273*4882a593Smuzhiyun #define VIVS_GL_FLUSH_CACHE_UNK11				0x00000800
274*4882a593Smuzhiyun #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK12			0x00001000
275*4882a593Smuzhiyun #define VIVS_GL_FLUSH_CACHE_DESCRIPTOR_UNK13			0x00002000
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun #define VIVS_GL_FLUSH_MMU					0x00003810
278*4882a593Smuzhiyun #define VIVS_GL_FLUSH_MMU_FLUSH_FEMMU				0x00000001
279*4882a593Smuzhiyun #define VIVS_GL_FLUSH_MMU_FLUSH_UNK1				0x00000002
280*4882a593Smuzhiyun #define VIVS_GL_FLUSH_MMU_FLUSH_UNK2				0x00000004
281*4882a593Smuzhiyun #define VIVS_GL_FLUSH_MMU_FLUSH_PEMMU				0x00000008
282*4882a593Smuzhiyun #define VIVS_GL_FLUSH_MMU_FLUSH_UNK4				0x00000010
283*4882a593Smuzhiyun 
284*4882a593Smuzhiyun #define VIVS_GL_VERTEX_ELEMENT_CONFIG				0x00003814
285*4882a593Smuzhiyun 
286*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG				0x00003818
287*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__MASK		0x00000003
288*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES__SHIFT		0
289*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_NONE		0x00000000
290*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_2X		0x00000001
291*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_4X		0x00000002
292*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_SAMPLES_MASK		0x00000008
293*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK		0x000000f0
294*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT		4
295*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES(x)		(((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES__MASK)
296*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_MSAA_ENABLES_MASK		0x00000100
297*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK			0x00007000
298*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT		12
299*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12(x)			(((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12__MASK)
300*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK12_MASK			0x00008000
301*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK			0x00030000
302*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT		16
303*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16(x)			(((x) << VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__SHIFT) & VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16__MASK)
304*4882a593Smuzhiyun #define VIVS_GL_MULTI_SAMPLE_CONFIG_UNK16_MASK			0x00080000
305*4882a593Smuzhiyun 
306*4882a593Smuzhiyun #define VIVS_GL_VARYING_TOTAL_COMPONENTS			0x0000381c
307*4882a593Smuzhiyun #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK		0x000000ff
308*4882a593Smuzhiyun #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT		0
309*4882a593Smuzhiyun #define VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM(x)			(((x) << VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__SHIFT) & VIVS_GL_VARYING_TOTAL_COMPONENTS_NUM__MASK)
310*4882a593Smuzhiyun 
311*4882a593Smuzhiyun #define VIVS_GL_VARYING_NUM_COMPONENTS				0x00003820
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun #define VIVS_GL_OCCLUSION_QUERY_ADDR				0x00003824
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE(i0)		       (0x00003828 + 0x4*(i0))
316*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE__ESIZE			0x00000004
317*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE__LEN			0x00000002
318*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK		0x00000003
319*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT		0
320*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP0(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP0__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP0__MASK)
321*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK		0x0000000c
322*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT		2
323*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP1(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP1__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP1__MASK)
324*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK		0x00000030
325*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT		4
326*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP2(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP2__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP2__MASK)
327*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK		0x000000c0
328*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT		6
329*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP3(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP3__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP3__MASK)
330*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK		0x00000300
331*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT		8
332*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP4(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP4__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP4__MASK)
333*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK		0x00000c00
334*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT		10
335*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP5(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP5__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP5__MASK)
336*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK		0x00003000
337*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT		12
338*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP6(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP6__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP6__MASK)
339*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK		0x0000c000
340*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT		14
341*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP7(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP7__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP7__MASK)
342*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK		0x00030000
343*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT		16
344*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP8(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP8__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP8__MASK)
345*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK		0x000c0000
346*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT		18
347*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP9(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP9__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP9__MASK)
348*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK		0x00300000
349*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT		20
350*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP10(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP10__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP10__MASK)
351*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK		0x00c00000
352*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT		22
353*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP11(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP11__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP11__MASK)
354*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK		0x03000000
355*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT		24
356*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP12(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP12__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP12__MASK)
357*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK		0x0c000000
358*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT		26
359*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP13(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP13__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP13__MASK)
360*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK		0x30000000
361*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT		28
362*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP14(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP14__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP14__MASK)
363*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK		0xc0000000
364*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT		30
365*4882a593Smuzhiyun #define VIVS_GL_VARYING_COMPONENT_USE_COMP15(x)			(((x) << VIVS_GL_VARYING_COMPONENT_USE_COMP15__SHIFT) & VIVS_GL_VARYING_COMPONENT_USE_COMP15__MASK)
366*4882a593Smuzhiyun 
367*4882a593Smuzhiyun #define VIVS_GL_UNK0382C					0x0000382c
368*4882a593Smuzhiyun 
369*4882a593Smuzhiyun #define VIVS_GL_OCCLUSION_QUERY_CONTROL				0x00003830
370*4882a593Smuzhiyun 
371*4882a593Smuzhiyun #define VIVS_GL_UNK03834					0x00003834
372*4882a593Smuzhiyun 
373*4882a593Smuzhiyun #define VIVS_GL_UNK03838					0x00003838
374*4882a593Smuzhiyun 
375*4882a593Smuzhiyun #define VIVS_GL_API_MODE					0x0000384c
376*4882a593Smuzhiyun #define VIVS_GL_API_MODE_OPENGL					0x00000000
377*4882a593Smuzhiyun #define VIVS_GL_API_MODE_OPENVG					0x00000001
378*4882a593Smuzhiyun #define VIVS_GL_API_MODE_OPENCL					0x00000002
379*4882a593Smuzhiyun 
380*4882a593Smuzhiyun #define VIVS_GL_CONTEXT_POINTER					0x00003850
381*4882a593Smuzhiyun 
382*4882a593Smuzhiyun #define VIVS_GL_UNK03854					0x00003854
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun #define VIVS_GL_BUG_FIXES					0x00003860
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun #define VIVS_GL_FENCE_OUT_ADDRESS				0x00003868
387*4882a593Smuzhiyun 
388*4882a593Smuzhiyun #define VIVS_GL_FENCE_OUT_DATA_LOW				0x0000386c
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun #define VIVS_GL_HALTI5_UNK03884					0x00003884
391*4882a593Smuzhiyun 
392*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS				0x00003888
393*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK		0x0000007f
394*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT		0
395*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT(x)		(((x) << VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_VS_PSIZE_OUT__MASK)
396*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK		0x00007f00
397*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT		8
398*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN(x)		(((x) << VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_PS_PCOORD_IN__MASK)
399*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK			0x007f0000
400*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT			16
401*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS_UNK16(x)			(((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK16__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK16__MASK)
402*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK			0xff000000
403*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT			24
404*4882a593Smuzhiyun #define VIVS_GL_HALTI5_SH_SPECIALS_UNK24(x)			(((x) << VIVS_GL_HALTI5_SH_SPECIALS_UNK24__SHIFT) & VIVS_GL_HALTI5_SH_SPECIALS_UNK24__MASK)
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun #define VIVS_GL_GS_UNK0388C					0x0000388c
407*4882a593Smuzhiyun 
408*4882a593Smuzhiyun #define VIVS_GL_FENCE_OUT_DATA_HIGH				0x00003898
409*4882a593Smuzhiyun 
410*4882a593Smuzhiyun #define VIVS_GL_SHADER_INDEX					0x0000389c
411*4882a593Smuzhiyun 
412*4882a593Smuzhiyun #define VIVS_GL_GS_UNK038A0(i0)				       (0x000038a0 + 0x4*(i0))
413*4882a593Smuzhiyun #define VIVS_GL_GS_UNK038A0__ESIZE				0x00000004
414*4882a593Smuzhiyun #define VIVS_GL_GS_UNK038A0__LEN				0x00000008
415*4882a593Smuzhiyun 
416*4882a593Smuzhiyun #define VIVS_GL_HALTI5_UNK038C0(i0)			       (0x000038c0 + 0x4*(i0))
417*4882a593Smuzhiyun #define VIVS_GL_HALTI5_UNK038C0__ESIZE				0x00000004
418*4882a593Smuzhiyun #define VIVS_GL_HALTI5_UNK038C0__LEN				0x00000010
419*4882a593Smuzhiyun 
420*4882a593Smuzhiyun #define VIVS_GL_SECURITY_UNK3900				0x00003900
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun #define VIVS_GL_SECURITY_UNK3904				0x00003904
423*4882a593Smuzhiyun 
424*4882a593Smuzhiyun #define VIVS_GL_UNK03A00					0x00003a00
425*4882a593Smuzhiyun 
426*4882a593Smuzhiyun #define VIVS_GL_UNK03A04					0x00003a04
427*4882a593Smuzhiyun 
428*4882a593Smuzhiyun #define VIVS_GL_UNK03A08					0x00003a08
429*4882a593Smuzhiyun 
430*4882a593Smuzhiyun #define VIVS_GL_UNK03A0C					0x00003a0c
431*4882a593Smuzhiyun 
432*4882a593Smuzhiyun #define VIVS_GL_UNK03A10					0x00003a10
433*4882a593Smuzhiyun 
434*4882a593Smuzhiyun #define VIVS_GL_STALL_TOKEN					0x00003c00
435*4882a593Smuzhiyun #define VIVS_GL_STALL_TOKEN_FROM__MASK				0x0000001f
436*4882a593Smuzhiyun #define VIVS_GL_STALL_TOKEN_FROM__SHIFT				0
437*4882a593Smuzhiyun #define VIVS_GL_STALL_TOKEN_FROM(x)				(((x) << VIVS_GL_STALL_TOKEN_FROM__SHIFT) & VIVS_GL_STALL_TOKEN_FROM__MASK)
438*4882a593Smuzhiyun #define VIVS_GL_STALL_TOKEN_TO__MASK				0x00001f00
439*4882a593Smuzhiyun #define VIVS_GL_STALL_TOKEN_TO__SHIFT				8
440*4882a593Smuzhiyun #define VIVS_GL_STALL_TOKEN_TO(x)				(((x) << VIVS_GL_STALL_TOKEN_TO__SHIFT) & VIVS_GL_STALL_TOKEN_TO__MASK)
441*4882a593Smuzhiyun #define VIVS_GL_STALL_TOKEN_FLIP0				0x40000000
442*4882a593Smuzhiyun #define VIVS_GL_STALL_TOKEN_FLIP1				0x80000000
443*4882a593Smuzhiyun 
444*4882a593Smuzhiyun #define VIVS_NFE						0x00000000
445*4882a593Smuzhiyun 
446*4882a593Smuzhiyun #define VIVS_NFE_VERTEX_STREAMS(i0)			       (0x00000000 + 0x4*(i0))
447*4882a593Smuzhiyun #define VIVS_NFE_VERTEX_STREAMS__ESIZE				0x00000004
448*4882a593Smuzhiyun #define VIVS_NFE_VERTEX_STREAMS__LEN				0x00000010
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun #define VIVS_NFE_VERTEX_STREAMS_BASE_ADDR(i0)		       (0x00014600 + 0x4*(i0))
451*4882a593Smuzhiyun 
452*4882a593Smuzhiyun #define VIVS_NFE_VERTEX_STREAMS_CONTROL(i0)		       (0x00014640 + 0x4*(i0))
453*4882a593Smuzhiyun 
454*4882a593Smuzhiyun #define VIVS_NFE_VERTEX_STREAMS_UNK14680(i0)		       (0x00014680 + 0x4*(i0))
455*4882a593Smuzhiyun 
456*4882a593Smuzhiyun #define VIVS_NFE_VERTEX_STREAMS_ROBUSTNESS_UNK146C0(i0)	       (0x000146c0 + 0x4*(i0))
457*4882a593Smuzhiyun 
458*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB(i0)			       (0x00000000 + 0x4*(i0))
459*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB__ESIZE				0x00000004
460*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB__LEN				0x00000020
461*4882a593Smuzhiyun 
462*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0(i0)		       (0x00017800 + 0x4*(i0))
463*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK		0x0000000f
464*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT		0
465*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE(x)			(((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_TYPE__MASK)
466*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK		0x00000030
467*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT		4
468*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN(x)		(((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_ENDIAN__MASK)
469*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK		0x00000700
470*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT		8
471*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM(x)		(((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_STREAM__MASK)
472*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK		0x00003000
473*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT		12
474*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM(x)			(((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NUM__MASK)
475*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__MASK		0x0000c000
476*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE__SHIFT	14
477*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_OFF		0x00000000
478*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_NORMALIZE_ON		0x00008000
479*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK		0x00ff0000
480*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT		16
481*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START(x)		(((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG0_START__MASK)
482*4882a593Smuzhiyun 
483*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_UNK17880(i0)		       (0x00017880 + 0x4*(i0))
484*4882a593Smuzhiyun 
485*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_UNK17900(i0)		       (0x00017900 + 0x4*(i0))
486*4882a593Smuzhiyun 
487*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_UNK17980(i0)		       (0x00017980 + 0x4*(i0))
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_SCALE(i0)		       (0x00017a00 + 0x4*(i0))
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1(i0)		       (0x00017a80 + 0x4*(i0))
492*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK		0x000000ff
493*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT		0
494*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END(x)			(((x) << VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__SHIFT) & VIVS_NFE_GENERIC_ATTRIB_CONFIG1_END__MASK)
495*4882a593Smuzhiyun #define VIVS_NFE_GENERIC_ATTRIB_CONFIG1_NONCONSECUTIVE		0x00000800
496*4882a593Smuzhiyun 
497*4882a593Smuzhiyun #define VIVS_DUMMY						0x00000000
498*4882a593Smuzhiyun 
499*4882a593Smuzhiyun #define VIVS_DUMMY_DUMMY					0x0003fffc
500*4882a593Smuzhiyun 
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun #endif /* STATE_XML */
503