1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Copyright (C) 2015-2018 Etnaviv Project
4*4882a593Smuzhiyun */
5*4882a593Smuzhiyun
6*4882a593Smuzhiyun #include <linux/component.h>
7*4882a593Smuzhiyun #include <linux/dma-mapping.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/of_platform.h>
10*4882a593Smuzhiyun #include <linux/uaccess.h>
11*4882a593Smuzhiyun
12*4882a593Smuzhiyun #include <drm/drm_debugfs.h>
13*4882a593Smuzhiyun #include <drm/drm_drv.h>
14*4882a593Smuzhiyun #include <drm/drm_file.h>
15*4882a593Smuzhiyun #include <drm/drm_ioctl.h>
16*4882a593Smuzhiyun #include <drm/drm_of.h>
17*4882a593Smuzhiyun #include <drm/drm_prime.h>
18*4882a593Smuzhiyun
19*4882a593Smuzhiyun #include "etnaviv_cmdbuf.h"
20*4882a593Smuzhiyun #include "etnaviv_drv.h"
21*4882a593Smuzhiyun #include "etnaviv_gpu.h"
22*4882a593Smuzhiyun #include "etnaviv_gem.h"
23*4882a593Smuzhiyun #include "etnaviv_mmu.h"
24*4882a593Smuzhiyun #include "etnaviv_perfmon.h"
25*4882a593Smuzhiyun
26*4882a593Smuzhiyun /*
27*4882a593Smuzhiyun * DRM operations:
28*4882a593Smuzhiyun */
29*4882a593Smuzhiyun
30*4882a593Smuzhiyun
load_gpu(struct drm_device * dev)31*4882a593Smuzhiyun static void load_gpu(struct drm_device *dev)
32*4882a593Smuzhiyun {
33*4882a593Smuzhiyun struct etnaviv_drm_private *priv = dev->dev_private;
34*4882a593Smuzhiyun unsigned int i;
35*4882a593Smuzhiyun
36*4882a593Smuzhiyun for (i = 0; i < ETNA_MAX_PIPES; i++) {
37*4882a593Smuzhiyun struct etnaviv_gpu *g = priv->gpu[i];
38*4882a593Smuzhiyun
39*4882a593Smuzhiyun if (g) {
40*4882a593Smuzhiyun int ret;
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun ret = etnaviv_gpu_init(g);
43*4882a593Smuzhiyun if (ret)
44*4882a593Smuzhiyun priv->gpu[i] = NULL;
45*4882a593Smuzhiyun }
46*4882a593Smuzhiyun }
47*4882a593Smuzhiyun }
48*4882a593Smuzhiyun
etnaviv_open(struct drm_device * dev,struct drm_file * file)49*4882a593Smuzhiyun static int etnaviv_open(struct drm_device *dev, struct drm_file *file)
50*4882a593Smuzhiyun {
51*4882a593Smuzhiyun struct etnaviv_drm_private *priv = dev->dev_private;
52*4882a593Smuzhiyun struct etnaviv_file_private *ctx;
53*4882a593Smuzhiyun int ret, i;
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
56*4882a593Smuzhiyun if (!ctx)
57*4882a593Smuzhiyun return -ENOMEM;
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun ctx->mmu = etnaviv_iommu_context_init(priv->mmu_global,
60*4882a593Smuzhiyun priv->cmdbuf_suballoc);
61*4882a593Smuzhiyun if (!ctx->mmu) {
62*4882a593Smuzhiyun ret = -ENOMEM;
63*4882a593Smuzhiyun goto out_free;
64*4882a593Smuzhiyun }
65*4882a593Smuzhiyun
66*4882a593Smuzhiyun for (i = 0; i < ETNA_MAX_PIPES; i++) {
67*4882a593Smuzhiyun struct etnaviv_gpu *gpu = priv->gpu[i];
68*4882a593Smuzhiyun struct drm_gpu_scheduler *sched;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun if (gpu) {
71*4882a593Smuzhiyun sched = &gpu->sched;
72*4882a593Smuzhiyun drm_sched_entity_init(&ctx->sched_entity[i],
73*4882a593Smuzhiyun DRM_SCHED_PRIORITY_NORMAL, &sched,
74*4882a593Smuzhiyun 1, NULL);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun }
77*4882a593Smuzhiyun
78*4882a593Smuzhiyun file->driver_priv = ctx;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return 0;
81*4882a593Smuzhiyun
82*4882a593Smuzhiyun out_free:
83*4882a593Smuzhiyun kfree(ctx);
84*4882a593Smuzhiyun return ret;
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
etnaviv_postclose(struct drm_device * dev,struct drm_file * file)87*4882a593Smuzhiyun static void etnaviv_postclose(struct drm_device *dev, struct drm_file *file)
88*4882a593Smuzhiyun {
89*4882a593Smuzhiyun struct etnaviv_drm_private *priv = dev->dev_private;
90*4882a593Smuzhiyun struct etnaviv_file_private *ctx = file->driver_priv;
91*4882a593Smuzhiyun unsigned int i;
92*4882a593Smuzhiyun
93*4882a593Smuzhiyun for (i = 0; i < ETNA_MAX_PIPES; i++) {
94*4882a593Smuzhiyun struct etnaviv_gpu *gpu = priv->gpu[i];
95*4882a593Smuzhiyun
96*4882a593Smuzhiyun if (gpu)
97*4882a593Smuzhiyun drm_sched_entity_destroy(&ctx->sched_entity[i]);
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun etnaviv_iommu_context_put(ctx->mmu);
101*4882a593Smuzhiyun
102*4882a593Smuzhiyun kfree(ctx);
103*4882a593Smuzhiyun }
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun /*
106*4882a593Smuzhiyun * DRM debugfs:
107*4882a593Smuzhiyun */
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
etnaviv_gem_show(struct drm_device * dev,struct seq_file * m)110*4882a593Smuzhiyun static int etnaviv_gem_show(struct drm_device *dev, struct seq_file *m)
111*4882a593Smuzhiyun {
112*4882a593Smuzhiyun struct etnaviv_drm_private *priv = dev->dev_private;
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun etnaviv_gem_describe_objects(priv, m);
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun return 0;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
etnaviv_mm_show(struct drm_device * dev,struct seq_file * m)119*4882a593Smuzhiyun static int etnaviv_mm_show(struct drm_device *dev, struct seq_file *m)
120*4882a593Smuzhiyun {
121*4882a593Smuzhiyun struct drm_printer p = drm_seq_file_printer(m);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun read_lock(&dev->vma_offset_manager->vm_lock);
124*4882a593Smuzhiyun drm_mm_print(&dev->vma_offset_manager->vm_addr_space_mm, &p);
125*4882a593Smuzhiyun read_unlock(&dev->vma_offset_manager->vm_lock);
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun return 0;
128*4882a593Smuzhiyun }
129*4882a593Smuzhiyun
etnaviv_mmu_show(struct etnaviv_gpu * gpu,struct seq_file * m)130*4882a593Smuzhiyun static int etnaviv_mmu_show(struct etnaviv_gpu *gpu, struct seq_file *m)
131*4882a593Smuzhiyun {
132*4882a593Smuzhiyun struct drm_printer p = drm_seq_file_printer(m);
133*4882a593Smuzhiyun struct etnaviv_iommu_context *mmu_context;
134*4882a593Smuzhiyun
135*4882a593Smuzhiyun seq_printf(m, "Active Objects (%s):\n", dev_name(gpu->dev));
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun /*
138*4882a593Smuzhiyun * Lock the GPU to avoid a MMU context switch just now and elevate
139*4882a593Smuzhiyun * the refcount of the current context to avoid it disappearing from
140*4882a593Smuzhiyun * under our feet.
141*4882a593Smuzhiyun */
142*4882a593Smuzhiyun mutex_lock(&gpu->lock);
143*4882a593Smuzhiyun mmu_context = gpu->mmu_context;
144*4882a593Smuzhiyun if (mmu_context)
145*4882a593Smuzhiyun etnaviv_iommu_context_get(mmu_context);
146*4882a593Smuzhiyun mutex_unlock(&gpu->lock);
147*4882a593Smuzhiyun
148*4882a593Smuzhiyun if (!mmu_context)
149*4882a593Smuzhiyun return 0;
150*4882a593Smuzhiyun
151*4882a593Smuzhiyun mutex_lock(&mmu_context->lock);
152*4882a593Smuzhiyun drm_mm_print(&mmu_context->mm, &p);
153*4882a593Smuzhiyun mutex_unlock(&mmu_context->lock);
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun etnaviv_iommu_context_put(mmu_context);
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun return 0;
158*4882a593Smuzhiyun }
159*4882a593Smuzhiyun
etnaviv_buffer_dump(struct etnaviv_gpu * gpu,struct seq_file * m)160*4882a593Smuzhiyun static void etnaviv_buffer_dump(struct etnaviv_gpu *gpu, struct seq_file *m)
161*4882a593Smuzhiyun {
162*4882a593Smuzhiyun struct etnaviv_cmdbuf *buf = &gpu->buffer;
163*4882a593Smuzhiyun u32 size = buf->size;
164*4882a593Smuzhiyun u32 *ptr = buf->vaddr;
165*4882a593Smuzhiyun u32 i;
166*4882a593Smuzhiyun
167*4882a593Smuzhiyun seq_printf(m, "virt %p - phys 0x%llx - free 0x%08x\n",
168*4882a593Smuzhiyun buf->vaddr, (u64)etnaviv_cmdbuf_get_pa(buf),
169*4882a593Smuzhiyun size - buf->user_size);
170*4882a593Smuzhiyun
171*4882a593Smuzhiyun for (i = 0; i < size / 4; i++) {
172*4882a593Smuzhiyun if (i && !(i % 4))
173*4882a593Smuzhiyun seq_puts(m, "\n");
174*4882a593Smuzhiyun if (i % 4 == 0)
175*4882a593Smuzhiyun seq_printf(m, "\t0x%p: ", ptr + i);
176*4882a593Smuzhiyun seq_printf(m, "%08x ", *(ptr + i));
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun seq_puts(m, "\n");
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
etnaviv_ring_show(struct etnaviv_gpu * gpu,struct seq_file * m)181*4882a593Smuzhiyun static int etnaviv_ring_show(struct etnaviv_gpu *gpu, struct seq_file *m)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun seq_printf(m, "Ring Buffer (%s): ", dev_name(gpu->dev));
184*4882a593Smuzhiyun
185*4882a593Smuzhiyun mutex_lock(&gpu->lock);
186*4882a593Smuzhiyun etnaviv_buffer_dump(gpu, m);
187*4882a593Smuzhiyun mutex_unlock(&gpu->lock);
188*4882a593Smuzhiyun
189*4882a593Smuzhiyun return 0;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
show_unlocked(struct seq_file * m,void * arg)192*4882a593Smuzhiyun static int show_unlocked(struct seq_file *m, void *arg)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun struct drm_info_node *node = (struct drm_info_node *) m->private;
195*4882a593Smuzhiyun struct drm_device *dev = node->minor->dev;
196*4882a593Smuzhiyun int (*show)(struct drm_device *dev, struct seq_file *m) =
197*4882a593Smuzhiyun node->info_ent->data;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun return show(dev, m);
200*4882a593Smuzhiyun }
201*4882a593Smuzhiyun
show_each_gpu(struct seq_file * m,void * arg)202*4882a593Smuzhiyun static int show_each_gpu(struct seq_file *m, void *arg)
203*4882a593Smuzhiyun {
204*4882a593Smuzhiyun struct drm_info_node *node = (struct drm_info_node *) m->private;
205*4882a593Smuzhiyun struct drm_device *dev = node->minor->dev;
206*4882a593Smuzhiyun struct etnaviv_drm_private *priv = dev->dev_private;
207*4882a593Smuzhiyun struct etnaviv_gpu *gpu;
208*4882a593Smuzhiyun int (*show)(struct etnaviv_gpu *gpu, struct seq_file *m) =
209*4882a593Smuzhiyun node->info_ent->data;
210*4882a593Smuzhiyun unsigned int i;
211*4882a593Smuzhiyun int ret = 0;
212*4882a593Smuzhiyun
213*4882a593Smuzhiyun for (i = 0; i < ETNA_MAX_PIPES; i++) {
214*4882a593Smuzhiyun gpu = priv->gpu[i];
215*4882a593Smuzhiyun if (!gpu)
216*4882a593Smuzhiyun continue;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun ret = show(gpu, m);
219*4882a593Smuzhiyun if (ret < 0)
220*4882a593Smuzhiyun break;
221*4882a593Smuzhiyun }
222*4882a593Smuzhiyun
223*4882a593Smuzhiyun return ret;
224*4882a593Smuzhiyun }
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun static struct drm_info_list etnaviv_debugfs_list[] = {
227*4882a593Smuzhiyun {"gpu", show_each_gpu, 0, etnaviv_gpu_debugfs},
228*4882a593Smuzhiyun {"gem", show_unlocked, 0, etnaviv_gem_show},
229*4882a593Smuzhiyun { "mm", show_unlocked, 0, etnaviv_mm_show },
230*4882a593Smuzhiyun {"mmu", show_each_gpu, 0, etnaviv_mmu_show},
231*4882a593Smuzhiyun {"ring", show_each_gpu, 0, etnaviv_ring_show},
232*4882a593Smuzhiyun };
233*4882a593Smuzhiyun
etnaviv_debugfs_init(struct drm_minor * minor)234*4882a593Smuzhiyun static void etnaviv_debugfs_init(struct drm_minor *minor)
235*4882a593Smuzhiyun {
236*4882a593Smuzhiyun drm_debugfs_create_files(etnaviv_debugfs_list,
237*4882a593Smuzhiyun ARRAY_SIZE(etnaviv_debugfs_list),
238*4882a593Smuzhiyun minor->debugfs_root, minor);
239*4882a593Smuzhiyun }
240*4882a593Smuzhiyun #endif
241*4882a593Smuzhiyun
242*4882a593Smuzhiyun /*
243*4882a593Smuzhiyun * DRM ioctls:
244*4882a593Smuzhiyun */
245*4882a593Smuzhiyun
etnaviv_ioctl_get_param(struct drm_device * dev,void * data,struct drm_file * file)246*4882a593Smuzhiyun static int etnaviv_ioctl_get_param(struct drm_device *dev, void *data,
247*4882a593Smuzhiyun struct drm_file *file)
248*4882a593Smuzhiyun {
249*4882a593Smuzhiyun struct etnaviv_drm_private *priv = dev->dev_private;
250*4882a593Smuzhiyun struct drm_etnaviv_param *args = data;
251*4882a593Smuzhiyun struct etnaviv_gpu *gpu;
252*4882a593Smuzhiyun
253*4882a593Smuzhiyun if (args->pipe >= ETNA_MAX_PIPES)
254*4882a593Smuzhiyun return -EINVAL;
255*4882a593Smuzhiyun
256*4882a593Smuzhiyun gpu = priv->gpu[args->pipe];
257*4882a593Smuzhiyun if (!gpu)
258*4882a593Smuzhiyun return -ENXIO;
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun return etnaviv_gpu_get_param(gpu, args->param, &args->value);
261*4882a593Smuzhiyun }
262*4882a593Smuzhiyun
etnaviv_ioctl_gem_new(struct drm_device * dev,void * data,struct drm_file * file)263*4882a593Smuzhiyun static int etnaviv_ioctl_gem_new(struct drm_device *dev, void *data,
264*4882a593Smuzhiyun struct drm_file *file)
265*4882a593Smuzhiyun {
266*4882a593Smuzhiyun struct drm_etnaviv_gem_new *args = data;
267*4882a593Smuzhiyun
268*4882a593Smuzhiyun if (args->flags & ~(ETNA_BO_CACHED | ETNA_BO_WC | ETNA_BO_UNCACHED |
269*4882a593Smuzhiyun ETNA_BO_FORCE_MMU))
270*4882a593Smuzhiyun return -EINVAL;
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun return etnaviv_gem_new_handle(dev, file, args->size,
273*4882a593Smuzhiyun args->flags, &args->handle);
274*4882a593Smuzhiyun }
275*4882a593Smuzhiyun
etnaviv_ioctl_gem_cpu_prep(struct drm_device * dev,void * data,struct drm_file * file)276*4882a593Smuzhiyun static int etnaviv_ioctl_gem_cpu_prep(struct drm_device *dev, void *data,
277*4882a593Smuzhiyun struct drm_file *file)
278*4882a593Smuzhiyun {
279*4882a593Smuzhiyun struct drm_etnaviv_gem_cpu_prep *args = data;
280*4882a593Smuzhiyun struct drm_gem_object *obj;
281*4882a593Smuzhiyun int ret;
282*4882a593Smuzhiyun
283*4882a593Smuzhiyun if (args->op & ~(ETNA_PREP_READ | ETNA_PREP_WRITE | ETNA_PREP_NOSYNC))
284*4882a593Smuzhiyun return -EINVAL;
285*4882a593Smuzhiyun
286*4882a593Smuzhiyun obj = drm_gem_object_lookup(file, args->handle);
287*4882a593Smuzhiyun if (!obj)
288*4882a593Smuzhiyun return -ENOENT;
289*4882a593Smuzhiyun
290*4882a593Smuzhiyun ret = etnaviv_gem_cpu_prep(obj, args->op, &args->timeout);
291*4882a593Smuzhiyun
292*4882a593Smuzhiyun drm_gem_object_put(obj);
293*4882a593Smuzhiyun
294*4882a593Smuzhiyun return ret;
295*4882a593Smuzhiyun }
296*4882a593Smuzhiyun
etnaviv_ioctl_gem_cpu_fini(struct drm_device * dev,void * data,struct drm_file * file)297*4882a593Smuzhiyun static int etnaviv_ioctl_gem_cpu_fini(struct drm_device *dev, void *data,
298*4882a593Smuzhiyun struct drm_file *file)
299*4882a593Smuzhiyun {
300*4882a593Smuzhiyun struct drm_etnaviv_gem_cpu_fini *args = data;
301*4882a593Smuzhiyun struct drm_gem_object *obj;
302*4882a593Smuzhiyun int ret;
303*4882a593Smuzhiyun
304*4882a593Smuzhiyun if (args->flags)
305*4882a593Smuzhiyun return -EINVAL;
306*4882a593Smuzhiyun
307*4882a593Smuzhiyun obj = drm_gem_object_lookup(file, args->handle);
308*4882a593Smuzhiyun if (!obj)
309*4882a593Smuzhiyun return -ENOENT;
310*4882a593Smuzhiyun
311*4882a593Smuzhiyun ret = etnaviv_gem_cpu_fini(obj);
312*4882a593Smuzhiyun
313*4882a593Smuzhiyun drm_gem_object_put(obj);
314*4882a593Smuzhiyun
315*4882a593Smuzhiyun return ret;
316*4882a593Smuzhiyun }
317*4882a593Smuzhiyun
etnaviv_ioctl_gem_info(struct drm_device * dev,void * data,struct drm_file * file)318*4882a593Smuzhiyun static int etnaviv_ioctl_gem_info(struct drm_device *dev, void *data,
319*4882a593Smuzhiyun struct drm_file *file)
320*4882a593Smuzhiyun {
321*4882a593Smuzhiyun struct drm_etnaviv_gem_info *args = data;
322*4882a593Smuzhiyun struct drm_gem_object *obj;
323*4882a593Smuzhiyun int ret;
324*4882a593Smuzhiyun
325*4882a593Smuzhiyun if (args->pad)
326*4882a593Smuzhiyun return -EINVAL;
327*4882a593Smuzhiyun
328*4882a593Smuzhiyun obj = drm_gem_object_lookup(file, args->handle);
329*4882a593Smuzhiyun if (!obj)
330*4882a593Smuzhiyun return -ENOENT;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun ret = etnaviv_gem_mmap_offset(obj, &args->offset);
333*4882a593Smuzhiyun drm_gem_object_put(obj);
334*4882a593Smuzhiyun
335*4882a593Smuzhiyun return ret;
336*4882a593Smuzhiyun }
337*4882a593Smuzhiyun
etnaviv_ioctl_wait_fence(struct drm_device * dev,void * data,struct drm_file * file)338*4882a593Smuzhiyun static int etnaviv_ioctl_wait_fence(struct drm_device *dev, void *data,
339*4882a593Smuzhiyun struct drm_file *file)
340*4882a593Smuzhiyun {
341*4882a593Smuzhiyun struct drm_etnaviv_wait_fence *args = data;
342*4882a593Smuzhiyun struct etnaviv_drm_private *priv = dev->dev_private;
343*4882a593Smuzhiyun struct drm_etnaviv_timespec *timeout = &args->timeout;
344*4882a593Smuzhiyun struct etnaviv_gpu *gpu;
345*4882a593Smuzhiyun
346*4882a593Smuzhiyun if (args->flags & ~(ETNA_WAIT_NONBLOCK))
347*4882a593Smuzhiyun return -EINVAL;
348*4882a593Smuzhiyun
349*4882a593Smuzhiyun if (args->pipe >= ETNA_MAX_PIPES)
350*4882a593Smuzhiyun return -EINVAL;
351*4882a593Smuzhiyun
352*4882a593Smuzhiyun gpu = priv->gpu[args->pipe];
353*4882a593Smuzhiyun if (!gpu)
354*4882a593Smuzhiyun return -ENXIO;
355*4882a593Smuzhiyun
356*4882a593Smuzhiyun if (args->flags & ETNA_WAIT_NONBLOCK)
357*4882a593Smuzhiyun timeout = NULL;
358*4882a593Smuzhiyun
359*4882a593Smuzhiyun return etnaviv_gpu_wait_fence_interruptible(gpu, args->fence,
360*4882a593Smuzhiyun timeout);
361*4882a593Smuzhiyun }
362*4882a593Smuzhiyun
etnaviv_ioctl_gem_userptr(struct drm_device * dev,void * data,struct drm_file * file)363*4882a593Smuzhiyun static int etnaviv_ioctl_gem_userptr(struct drm_device *dev, void *data,
364*4882a593Smuzhiyun struct drm_file *file)
365*4882a593Smuzhiyun {
366*4882a593Smuzhiyun struct drm_etnaviv_gem_userptr *args = data;
367*4882a593Smuzhiyun
368*4882a593Smuzhiyun if (args->flags & ~(ETNA_USERPTR_READ|ETNA_USERPTR_WRITE) ||
369*4882a593Smuzhiyun args->flags == 0)
370*4882a593Smuzhiyun return -EINVAL;
371*4882a593Smuzhiyun
372*4882a593Smuzhiyun if (offset_in_page(args->user_ptr | args->user_size) ||
373*4882a593Smuzhiyun (uintptr_t)args->user_ptr != args->user_ptr ||
374*4882a593Smuzhiyun (u32)args->user_size != args->user_size ||
375*4882a593Smuzhiyun args->user_ptr & ~PAGE_MASK)
376*4882a593Smuzhiyun return -EINVAL;
377*4882a593Smuzhiyun
378*4882a593Smuzhiyun if (!access_ok((void __user *)(unsigned long)args->user_ptr,
379*4882a593Smuzhiyun args->user_size))
380*4882a593Smuzhiyun return -EFAULT;
381*4882a593Smuzhiyun
382*4882a593Smuzhiyun return etnaviv_gem_new_userptr(dev, file, args->user_ptr,
383*4882a593Smuzhiyun args->user_size, args->flags,
384*4882a593Smuzhiyun &args->handle);
385*4882a593Smuzhiyun }
386*4882a593Smuzhiyun
etnaviv_ioctl_gem_wait(struct drm_device * dev,void * data,struct drm_file * file)387*4882a593Smuzhiyun static int etnaviv_ioctl_gem_wait(struct drm_device *dev, void *data,
388*4882a593Smuzhiyun struct drm_file *file)
389*4882a593Smuzhiyun {
390*4882a593Smuzhiyun struct etnaviv_drm_private *priv = dev->dev_private;
391*4882a593Smuzhiyun struct drm_etnaviv_gem_wait *args = data;
392*4882a593Smuzhiyun struct drm_etnaviv_timespec *timeout = &args->timeout;
393*4882a593Smuzhiyun struct drm_gem_object *obj;
394*4882a593Smuzhiyun struct etnaviv_gpu *gpu;
395*4882a593Smuzhiyun int ret;
396*4882a593Smuzhiyun
397*4882a593Smuzhiyun if (args->flags & ~(ETNA_WAIT_NONBLOCK))
398*4882a593Smuzhiyun return -EINVAL;
399*4882a593Smuzhiyun
400*4882a593Smuzhiyun if (args->pipe >= ETNA_MAX_PIPES)
401*4882a593Smuzhiyun return -EINVAL;
402*4882a593Smuzhiyun
403*4882a593Smuzhiyun gpu = priv->gpu[args->pipe];
404*4882a593Smuzhiyun if (!gpu)
405*4882a593Smuzhiyun return -ENXIO;
406*4882a593Smuzhiyun
407*4882a593Smuzhiyun obj = drm_gem_object_lookup(file, args->handle);
408*4882a593Smuzhiyun if (!obj)
409*4882a593Smuzhiyun return -ENOENT;
410*4882a593Smuzhiyun
411*4882a593Smuzhiyun if (args->flags & ETNA_WAIT_NONBLOCK)
412*4882a593Smuzhiyun timeout = NULL;
413*4882a593Smuzhiyun
414*4882a593Smuzhiyun ret = etnaviv_gem_wait_bo(gpu, obj, timeout);
415*4882a593Smuzhiyun
416*4882a593Smuzhiyun drm_gem_object_put(obj);
417*4882a593Smuzhiyun
418*4882a593Smuzhiyun return ret;
419*4882a593Smuzhiyun }
420*4882a593Smuzhiyun
etnaviv_ioctl_pm_query_dom(struct drm_device * dev,void * data,struct drm_file * file)421*4882a593Smuzhiyun static int etnaviv_ioctl_pm_query_dom(struct drm_device *dev, void *data,
422*4882a593Smuzhiyun struct drm_file *file)
423*4882a593Smuzhiyun {
424*4882a593Smuzhiyun struct etnaviv_drm_private *priv = dev->dev_private;
425*4882a593Smuzhiyun struct drm_etnaviv_pm_domain *args = data;
426*4882a593Smuzhiyun struct etnaviv_gpu *gpu;
427*4882a593Smuzhiyun
428*4882a593Smuzhiyun if (args->pipe >= ETNA_MAX_PIPES)
429*4882a593Smuzhiyun return -EINVAL;
430*4882a593Smuzhiyun
431*4882a593Smuzhiyun gpu = priv->gpu[args->pipe];
432*4882a593Smuzhiyun if (!gpu)
433*4882a593Smuzhiyun return -ENXIO;
434*4882a593Smuzhiyun
435*4882a593Smuzhiyun return etnaviv_pm_query_dom(gpu, args);
436*4882a593Smuzhiyun }
437*4882a593Smuzhiyun
etnaviv_ioctl_pm_query_sig(struct drm_device * dev,void * data,struct drm_file * file)438*4882a593Smuzhiyun static int etnaviv_ioctl_pm_query_sig(struct drm_device *dev, void *data,
439*4882a593Smuzhiyun struct drm_file *file)
440*4882a593Smuzhiyun {
441*4882a593Smuzhiyun struct etnaviv_drm_private *priv = dev->dev_private;
442*4882a593Smuzhiyun struct drm_etnaviv_pm_signal *args = data;
443*4882a593Smuzhiyun struct etnaviv_gpu *gpu;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun if (args->pipe >= ETNA_MAX_PIPES)
446*4882a593Smuzhiyun return -EINVAL;
447*4882a593Smuzhiyun
448*4882a593Smuzhiyun gpu = priv->gpu[args->pipe];
449*4882a593Smuzhiyun if (!gpu)
450*4882a593Smuzhiyun return -ENXIO;
451*4882a593Smuzhiyun
452*4882a593Smuzhiyun return etnaviv_pm_query_sig(gpu, args);
453*4882a593Smuzhiyun }
454*4882a593Smuzhiyun
455*4882a593Smuzhiyun static const struct drm_ioctl_desc etnaviv_ioctls[] = {
456*4882a593Smuzhiyun #define ETNA_IOCTL(n, func, flags) \
457*4882a593Smuzhiyun DRM_IOCTL_DEF_DRV(ETNAVIV_##n, etnaviv_ioctl_##func, flags)
458*4882a593Smuzhiyun ETNA_IOCTL(GET_PARAM, get_param, DRM_RENDER_ALLOW),
459*4882a593Smuzhiyun ETNA_IOCTL(GEM_NEW, gem_new, DRM_RENDER_ALLOW),
460*4882a593Smuzhiyun ETNA_IOCTL(GEM_INFO, gem_info, DRM_RENDER_ALLOW),
461*4882a593Smuzhiyun ETNA_IOCTL(GEM_CPU_PREP, gem_cpu_prep, DRM_RENDER_ALLOW),
462*4882a593Smuzhiyun ETNA_IOCTL(GEM_CPU_FINI, gem_cpu_fini, DRM_RENDER_ALLOW),
463*4882a593Smuzhiyun ETNA_IOCTL(GEM_SUBMIT, gem_submit, DRM_RENDER_ALLOW),
464*4882a593Smuzhiyun ETNA_IOCTL(WAIT_FENCE, wait_fence, DRM_RENDER_ALLOW),
465*4882a593Smuzhiyun ETNA_IOCTL(GEM_USERPTR, gem_userptr, DRM_RENDER_ALLOW),
466*4882a593Smuzhiyun ETNA_IOCTL(GEM_WAIT, gem_wait, DRM_RENDER_ALLOW),
467*4882a593Smuzhiyun ETNA_IOCTL(PM_QUERY_DOM, pm_query_dom, DRM_RENDER_ALLOW),
468*4882a593Smuzhiyun ETNA_IOCTL(PM_QUERY_SIG, pm_query_sig, DRM_RENDER_ALLOW),
469*4882a593Smuzhiyun };
470*4882a593Smuzhiyun
471*4882a593Smuzhiyun static const struct vm_operations_struct vm_ops = {
472*4882a593Smuzhiyun .fault = etnaviv_gem_fault,
473*4882a593Smuzhiyun .open = drm_gem_vm_open,
474*4882a593Smuzhiyun .close = drm_gem_vm_close,
475*4882a593Smuzhiyun };
476*4882a593Smuzhiyun
477*4882a593Smuzhiyun static const struct file_operations fops = {
478*4882a593Smuzhiyun .owner = THIS_MODULE,
479*4882a593Smuzhiyun .open = drm_open,
480*4882a593Smuzhiyun .release = drm_release,
481*4882a593Smuzhiyun .unlocked_ioctl = drm_ioctl,
482*4882a593Smuzhiyun .compat_ioctl = drm_compat_ioctl,
483*4882a593Smuzhiyun .poll = drm_poll,
484*4882a593Smuzhiyun .read = drm_read,
485*4882a593Smuzhiyun .llseek = no_llseek,
486*4882a593Smuzhiyun .mmap = etnaviv_gem_mmap,
487*4882a593Smuzhiyun };
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun static struct drm_driver etnaviv_drm_driver = {
490*4882a593Smuzhiyun .driver_features = DRIVER_GEM | DRIVER_RENDER,
491*4882a593Smuzhiyun .open = etnaviv_open,
492*4882a593Smuzhiyun .postclose = etnaviv_postclose,
493*4882a593Smuzhiyun .gem_free_object_unlocked = etnaviv_gem_free_object,
494*4882a593Smuzhiyun .gem_vm_ops = &vm_ops,
495*4882a593Smuzhiyun .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
496*4882a593Smuzhiyun .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
497*4882a593Smuzhiyun .gem_prime_pin = etnaviv_gem_prime_pin,
498*4882a593Smuzhiyun .gem_prime_unpin = etnaviv_gem_prime_unpin,
499*4882a593Smuzhiyun .gem_prime_get_sg_table = etnaviv_gem_prime_get_sg_table,
500*4882a593Smuzhiyun .gem_prime_import_sg_table = etnaviv_gem_prime_import_sg_table,
501*4882a593Smuzhiyun .gem_prime_vmap = etnaviv_gem_prime_vmap,
502*4882a593Smuzhiyun .gem_prime_vunmap = etnaviv_gem_prime_vunmap,
503*4882a593Smuzhiyun .gem_prime_mmap = etnaviv_gem_prime_mmap,
504*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS
505*4882a593Smuzhiyun .debugfs_init = etnaviv_debugfs_init,
506*4882a593Smuzhiyun #endif
507*4882a593Smuzhiyun .ioctls = etnaviv_ioctls,
508*4882a593Smuzhiyun .num_ioctls = DRM_ETNAVIV_NUM_IOCTLS,
509*4882a593Smuzhiyun .fops = &fops,
510*4882a593Smuzhiyun .name = "etnaviv",
511*4882a593Smuzhiyun .desc = "etnaviv DRM",
512*4882a593Smuzhiyun .date = "20151214",
513*4882a593Smuzhiyun .major = 1,
514*4882a593Smuzhiyun .minor = 3,
515*4882a593Smuzhiyun };
516*4882a593Smuzhiyun
517*4882a593Smuzhiyun /*
518*4882a593Smuzhiyun * Platform driver:
519*4882a593Smuzhiyun */
etnaviv_bind(struct device * dev)520*4882a593Smuzhiyun static int etnaviv_bind(struct device *dev)
521*4882a593Smuzhiyun {
522*4882a593Smuzhiyun struct etnaviv_drm_private *priv;
523*4882a593Smuzhiyun struct drm_device *drm;
524*4882a593Smuzhiyun int ret;
525*4882a593Smuzhiyun
526*4882a593Smuzhiyun drm = drm_dev_alloc(&etnaviv_drm_driver, dev);
527*4882a593Smuzhiyun if (IS_ERR(drm))
528*4882a593Smuzhiyun return PTR_ERR(drm);
529*4882a593Smuzhiyun
530*4882a593Smuzhiyun priv = kzalloc(sizeof(*priv), GFP_KERNEL);
531*4882a593Smuzhiyun if (!priv) {
532*4882a593Smuzhiyun dev_err(dev, "failed to allocate private data\n");
533*4882a593Smuzhiyun ret = -ENOMEM;
534*4882a593Smuzhiyun goto out_put;
535*4882a593Smuzhiyun }
536*4882a593Smuzhiyun drm->dev_private = priv;
537*4882a593Smuzhiyun
538*4882a593Smuzhiyun dev->dma_parms = &priv->dma_parms;
539*4882a593Smuzhiyun dma_set_max_seg_size(dev, SZ_2G);
540*4882a593Smuzhiyun
541*4882a593Smuzhiyun mutex_init(&priv->gem_lock);
542*4882a593Smuzhiyun INIT_LIST_HEAD(&priv->gem_list);
543*4882a593Smuzhiyun priv->num_gpus = 0;
544*4882a593Smuzhiyun priv->shm_gfp_mask = GFP_HIGHUSER | __GFP_RETRY_MAYFAIL | __GFP_NOWARN;
545*4882a593Smuzhiyun
546*4882a593Smuzhiyun priv->cmdbuf_suballoc = etnaviv_cmdbuf_suballoc_new(drm->dev);
547*4882a593Smuzhiyun if (IS_ERR(priv->cmdbuf_suballoc)) {
548*4882a593Smuzhiyun dev_err(drm->dev, "Failed to create cmdbuf suballocator\n");
549*4882a593Smuzhiyun ret = PTR_ERR(priv->cmdbuf_suballoc);
550*4882a593Smuzhiyun goto out_free_priv;
551*4882a593Smuzhiyun }
552*4882a593Smuzhiyun
553*4882a593Smuzhiyun dev_set_drvdata(dev, drm);
554*4882a593Smuzhiyun
555*4882a593Smuzhiyun ret = component_bind_all(dev, drm);
556*4882a593Smuzhiyun if (ret < 0)
557*4882a593Smuzhiyun goto out_destroy_suballoc;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun load_gpu(drm);
560*4882a593Smuzhiyun
561*4882a593Smuzhiyun ret = drm_dev_register(drm, 0);
562*4882a593Smuzhiyun if (ret)
563*4882a593Smuzhiyun goto out_unbind;
564*4882a593Smuzhiyun
565*4882a593Smuzhiyun return 0;
566*4882a593Smuzhiyun
567*4882a593Smuzhiyun out_unbind:
568*4882a593Smuzhiyun component_unbind_all(dev, drm);
569*4882a593Smuzhiyun out_destroy_suballoc:
570*4882a593Smuzhiyun etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc);
571*4882a593Smuzhiyun out_free_priv:
572*4882a593Smuzhiyun kfree(priv);
573*4882a593Smuzhiyun out_put:
574*4882a593Smuzhiyun drm_dev_put(drm);
575*4882a593Smuzhiyun
576*4882a593Smuzhiyun return ret;
577*4882a593Smuzhiyun }
578*4882a593Smuzhiyun
etnaviv_unbind(struct device * dev)579*4882a593Smuzhiyun static void etnaviv_unbind(struct device *dev)
580*4882a593Smuzhiyun {
581*4882a593Smuzhiyun struct drm_device *drm = dev_get_drvdata(dev);
582*4882a593Smuzhiyun struct etnaviv_drm_private *priv = drm->dev_private;
583*4882a593Smuzhiyun
584*4882a593Smuzhiyun drm_dev_unregister(drm);
585*4882a593Smuzhiyun
586*4882a593Smuzhiyun component_unbind_all(dev, drm);
587*4882a593Smuzhiyun
588*4882a593Smuzhiyun dev->dma_parms = NULL;
589*4882a593Smuzhiyun
590*4882a593Smuzhiyun etnaviv_cmdbuf_suballoc_destroy(priv->cmdbuf_suballoc);
591*4882a593Smuzhiyun
592*4882a593Smuzhiyun drm->dev_private = NULL;
593*4882a593Smuzhiyun kfree(priv);
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun drm_dev_put(drm);
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun static const struct component_master_ops etnaviv_master_ops = {
599*4882a593Smuzhiyun .bind = etnaviv_bind,
600*4882a593Smuzhiyun .unbind = etnaviv_unbind,
601*4882a593Smuzhiyun };
602*4882a593Smuzhiyun
compare_of(struct device * dev,void * data)603*4882a593Smuzhiyun static int compare_of(struct device *dev, void *data)
604*4882a593Smuzhiyun {
605*4882a593Smuzhiyun struct device_node *np = data;
606*4882a593Smuzhiyun
607*4882a593Smuzhiyun return dev->of_node == np;
608*4882a593Smuzhiyun }
609*4882a593Smuzhiyun
compare_str(struct device * dev,void * data)610*4882a593Smuzhiyun static int compare_str(struct device *dev, void *data)
611*4882a593Smuzhiyun {
612*4882a593Smuzhiyun return !strcmp(dev_name(dev), data);
613*4882a593Smuzhiyun }
614*4882a593Smuzhiyun
etnaviv_pdev_probe(struct platform_device * pdev)615*4882a593Smuzhiyun static int etnaviv_pdev_probe(struct platform_device *pdev)
616*4882a593Smuzhiyun {
617*4882a593Smuzhiyun struct device *dev = &pdev->dev;
618*4882a593Smuzhiyun struct component_match *match = NULL;
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun if (!dev->platform_data) {
621*4882a593Smuzhiyun struct device_node *core_node;
622*4882a593Smuzhiyun
623*4882a593Smuzhiyun for_each_compatible_node(core_node, NULL, "vivante,gc") {
624*4882a593Smuzhiyun if (!of_device_is_available(core_node))
625*4882a593Smuzhiyun continue;
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun drm_of_component_match_add(&pdev->dev, &match,
628*4882a593Smuzhiyun compare_of, core_node);
629*4882a593Smuzhiyun }
630*4882a593Smuzhiyun } else {
631*4882a593Smuzhiyun char **names = dev->platform_data;
632*4882a593Smuzhiyun unsigned i;
633*4882a593Smuzhiyun
634*4882a593Smuzhiyun for (i = 0; names[i]; i++)
635*4882a593Smuzhiyun component_match_add(dev, &match, compare_str, names[i]);
636*4882a593Smuzhiyun }
637*4882a593Smuzhiyun
638*4882a593Smuzhiyun return component_master_add_with_match(dev, &etnaviv_master_ops, match);
639*4882a593Smuzhiyun }
640*4882a593Smuzhiyun
etnaviv_pdev_remove(struct platform_device * pdev)641*4882a593Smuzhiyun static int etnaviv_pdev_remove(struct platform_device *pdev)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun component_master_del(&pdev->dev, &etnaviv_master_ops);
644*4882a593Smuzhiyun
645*4882a593Smuzhiyun return 0;
646*4882a593Smuzhiyun }
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun static struct platform_driver etnaviv_platform_driver = {
649*4882a593Smuzhiyun .probe = etnaviv_pdev_probe,
650*4882a593Smuzhiyun .remove = etnaviv_pdev_remove,
651*4882a593Smuzhiyun .driver = {
652*4882a593Smuzhiyun .name = "etnaviv",
653*4882a593Smuzhiyun },
654*4882a593Smuzhiyun };
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun static struct platform_device *etnaviv_drm;
657*4882a593Smuzhiyun
etnaviv_init(void)658*4882a593Smuzhiyun static int __init etnaviv_init(void)
659*4882a593Smuzhiyun {
660*4882a593Smuzhiyun struct platform_device *pdev;
661*4882a593Smuzhiyun int ret;
662*4882a593Smuzhiyun struct device_node *np;
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun etnaviv_validate_init();
665*4882a593Smuzhiyun
666*4882a593Smuzhiyun ret = platform_driver_register(&etnaviv_gpu_driver);
667*4882a593Smuzhiyun if (ret != 0)
668*4882a593Smuzhiyun return ret;
669*4882a593Smuzhiyun
670*4882a593Smuzhiyun ret = platform_driver_register(&etnaviv_platform_driver);
671*4882a593Smuzhiyun if (ret != 0)
672*4882a593Smuzhiyun goto unregister_gpu_driver;
673*4882a593Smuzhiyun
674*4882a593Smuzhiyun /*
675*4882a593Smuzhiyun * If the DT contains at least one available GPU device, instantiate
676*4882a593Smuzhiyun * the DRM platform device.
677*4882a593Smuzhiyun */
678*4882a593Smuzhiyun for_each_compatible_node(np, NULL, "vivante,gc") {
679*4882a593Smuzhiyun if (!of_device_is_available(np))
680*4882a593Smuzhiyun continue;
681*4882a593Smuzhiyun
682*4882a593Smuzhiyun pdev = platform_device_alloc("etnaviv", -1);
683*4882a593Smuzhiyun if (!pdev) {
684*4882a593Smuzhiyun ret = -ENOMEM;
685*4882a593Smuzhiyun of_node_put(np);
686*4882a593Smuzhiyun goto unregister_platform_driver;
687*4882a593Smuzhiyun }
688*4882a593Smuzhiyun pdev->dev.coherent_dma_mask = DMA_BIT_MASK(40);
689*4882a593Smuzhiyun pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
690*4882a593Smuzhiyun
691*4882a593Smuzhiyun /*
692*4882a593Smuzhiyun * Apply the same DMA configuration to the virtual etnaviv
693*4882a593Smuzhiyun * device as the GPU we found. This assumes that all Vivante
694*4882a593Smuzhiyun * GPUs in the system share the same DMA constraints.
695*4882a593Smuzhiyun */
696*4882a593Smuzhiyun of_dma_configure(&pdev->dev, np, true);
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun ret = platform_device_add(pdev);
699*4882a593Smuzhiyun if (ret) {
700*4882a593Smuzhiyun platform_device_put(pdev);
701*4882a593Smuzhiyun of_node_put(np);
702*4882a593Smuzhiyun goto unregister_platform_driver;
703*4882a593Smuzhiyun }
704*4882a593Smuzhiyun
705*4882a593Smuzhiyun etnaviv_drm = pdev;
706*4882a593Smuzhiyun of_node_put(np);
707*4882a593Smuzhiyun break;
708*4882a593Smuzhiyun }
709*4882a593Smuzhiyun
710*4882a593Smuzhiyun return 0;
711*4882a593Smuzhiyun
712*4882a593Smuzhiyun unregister_platform_driver:
713*4882a593Smuzhiyun platform_driver_unregister(&etnaviv_platform_driver);
714*4882a593Smuzhiyun unregister_gpu_driver:
715*4882a593Smuzhiyun platform_driver_unregister(&etnaviv_gpu_driver);
716*4882a593Smuzhiyun return ret;
717*4882a593Smuzhiyun }
718*4882a593Smuzhiyun module_init(etnaviv_init);
719*4882a593Smuzhiyun
etnaviv_exit(void)720*4882a593Smuzhiyun static void __exit etnaviv_exit(void)
721*4882a593Smuzhiyun {
722*4882a593Smuzhiyun platform_device_unregister(etnaviv_drm);
723*4882a593Smuzhiyun platform_driver_unregister(&etnaviv_platform_driver);
724*4882a593Smuzhiyun platform_driver_unregister(&etnaviv_gpu_driver);
725*4882a593Smuzhiyun }
726*4882a593Smuzhiyun module_exit(etnaviv_exit);
727*4882a593Smuzhiyun
728*4882a593Smuzhiyun MODULE_AUTHOR("Christian Gmeiner <christian.gmeiner@gmail.com>");
729*4882a593Smuzhiyun MODULE_AUTHOR("Russell King <rmk+kernel@armlinux.org.uk>");
730*4882a593Smuzhiyun MODULE_AUTHOR("Lucas Stach <l.stach@pengutronix.de>");
731*4882a593Smuzhiyun MODULE_DESCRIPTION("etnaviv DRM Driver");
732*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
733*4882a593Smuzhiyun MODULE_ALIAS("platform:etnaviv");
734