1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) Rockchip Electronics Co.Ltd 4*4882a593Smuzhiyun * Author: 5*4882a593Smuzhiyun * Algea Cao <algea.cao@rock-chips.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef __DW_HDMI_QP_H__ 8*4882a593Smuzhiyun #define __DW_HDMI_QP_H__ 9*4882a593Smuzhiyun /* Main Unit Registers */ 10*4882a593Smuzhiyun #define CORE_ID 0x0 11*4882a593Smuzhiyun #define VER_NUMBER 0x4 12*4882a593Smuzhiyun #define VER_TYPE 0x8 13*4882a593Smuzhiyun #define CONFIG_REG 0xc 14*4882a593Smuzhiyun #define CONFIG_CEC BIT(28) 15*4882a593Smuzhiyun #define CONFIG_AUD_UD BIT(23) 16*4882a593Smuzhiyun #define CORE_TIMESTAMP_HHMM 0x14 17*4882a593Smuzhiyun #define CORE_TIMESTAMP_MMDD 0x18 18*4882a593Smuzhiyun #define CORE_TIMESTAMP_YYYY 0x1c 19*4882a593Smuzhiyun /* Reset Manager Registers */ 20*4882a593Smuzhiyun #define GLOBAL_SWRESET_REQUEST 0x40 21*4882a593Smuzhiyun #define EARCRX_CMDC_SWINIT_P BIT(27) 22*4882a593Smuzhiyun #define AVP_DATAPATH_PACKET_AUDIO_SWINIT_P BIT(10) 23*4882a593Smuzhiyun #define GLOBAL_SWDISABLE 0x44 24*4882a593Smuzhiyun #define CEC_SWDISABLE BIT(17) 25*4882a593Smuzhiyun #define AVP_DATAPATH_PACKET_AUDIO_SWDISABLE BIT(10) 26*4882a593Smuzhiyun #define AVP_DATAPATH_VIDEO_SWDISABLE BIT(6) 27*4882a593Smuzhiyun #define RESET_MANAGER_CONFIG0 0x48 28*4882a593Smuzhiyun #define RESET_MANAGER_STATUS0 0x50 29*4882a593Smuzhiyun #define RESET_MANAGER_STATUS1 0x54 30*4882a593Smuzhiyun #define RESET_MANAGER_STATUS2 0x58 31*4882a593Smuzhiyun /* Timer Base Registers */ 32*4882a593Smuzhiyun #define TIMER_BASE_CONFIG0 0x80 33*4882a593Smuzhiyun #define TIMER_BASE_STATUS0 0x84 34*4882a593Smuzhiyun /* CMU Registers */ 35*4882a593Smuzhiyun #define CMU_CONFIG0 0xa0 36*4882a593Smuzhiyun #define CMU_CONFIG1 0xa4 37*4882a593Smuzhiyun #define CMU_CONFIG2 0xa8 38*4882a593Smuzhiyun #define CMU_CONFIG3 0xac 39*4882a593Smuzhiyun #define CMU_STATUS 0xb0 40*4882a593Smuzhiyun #define DISPLAY_CLK_MONITOR 0x3f 41*4882a593Smuzhiyun #define DISPLAY_CLK_LOCKED 0X15 42*4882a593Smuzhiyun #define EARC_BPCLK_OFF BIT(9) 43*4882a593Smuzhiyun #define AUDCLK_OFF BIT(7) 44*4882a593Smuzhiyun #define LINKQPCLK_OFF BIT(5) 45*4882a593Smuzhiyun #define VIDQPCLK_OFF BIT(3) 46*4882a593Smuzhiyun #define IPI_CLK_OFF BIT(1) 47*4882a593Smuzhiyun #define CMU_IPI_CLK_FREQ 0xb4 48*4882a593Smuzhiyun #define CMU_VIDQPCLK_FREQ 0xb8 49*4882a593Smuzhiyun #define CMU_LINKQPCLK_FREQ 0xbc 50*4882a593Smuzhiyun #define CMU_AUDQPCLK_FREQ 0xc0 51*4882a593Smuzhiyun #define CMU_EARC_BPCLK_FREQ 0xc4 52*4882a593Smuzhiyun /* I2CM Registers */ 53*4882a593Smuzhiyun #define I2CM_SM_SCL_CONFIG0 0xe0 54*4882a593Smuzhiyun #define I2CM_FM_SCL_CONFIG0 0xe4 55*4882a593Smuzhiyun #define I2CM_CONFIG0 0xe8 56*4882a593Smuzhiyun #define I2CM_CONTROL0 0xec 57*4882a593Smuzhiyun #define I2CM_STATUS0 0xf0 58*4882a593Smuzhiyun #define I2CM_INTERFACE_CONTROL0 0xf4 59*4882a593Smuzhiyun #define I2CM_ADDR 0xff000 60*4882a593Smuzhiyun #define I2CM_SLVADDR 0xfe0 61*4882a593Smuzhiyun #define I2CM_WR_MASK 0x1e 62*4882a593Smuzhiyun #define I2CM_EXT_READ BIT(4) 63*4882a593Smuzhiyun #define I2CM_SHORT_READ BIT(3) 64*4882a593Smuzhiyun #define I2CM_FM_READ BIT(2) 65*4882a593Smuzhiyun #define I2CM_FM_WRITE BIT(1) 66*4882a593Smuzhiyun #define I2CM_FM_EN BIT(0) 67*4882a593Smuzhiyun #define I2CM_INTERFACE_CONTROL1 0xf8 68*4882a593Smuzhiyun #define I2CM_SEG_PTR 0x7f80 69*4882a593Smuzhiyun #define I2CM_SEG_ADDR 0x7f 70*4882a593Smuzhiyun #define I2CM_INTERFACE_WRDATA_0_3 0xfc 71*4882a593Smuzhiyun #define I2CM_INTERFACE_WRDATA_4_7 0x100 72*4882a593Smuzhiyun #define I2CM_INTERFACE_WRDATA_8_11 0x104 73*4882a593Smuzhiyun #define I2CM_INTERFACE_WRDATA_12_15 0x108 74*4882a593Smuzhiyun #define I2CM_INTERFACE_RDDATA_0_3 0x10c 75*4882a593Smuzhiyun #define I2CM_INTERFACE_RDDATA_4_7 0x110 76*4882a593Smuzhiyun #define I2CM_INTERFACE_RDDATA_8_11 0x114 77*4882a593Smuzhiyun #define I2CM_INTERFACE_RDDATA_12_15 0x118 78*4882a593Smuzhiyun /* SCDC Registers */ 79*4882a593Smuzhiyun #define SCDC_CONFIG0 0x140 80*4882a593Smuzhiyun #define SCDC_I2C_FM_EN BIT(12) 81*4882a593Smuzhiyun #define SCDC_UPD_FLAGS_AUTO_CLR BIT(6) 82*4882a593Smuzhiyun #define SCDC_UPD_FLAGS_POLL_EN BIT(4) 83*4882a593Smuzhiyun #define SCDC_CONTROL0 0x148 84*4882a593Smuzhiyun #define SCDC_STATUS0 0x150 85*4882a593Smuzhiyun #define STATUS_UPDATE BIT(0) 86*4882a593Smuzhiyun #define FRL_START BIT(4) 87*4882a593Smuzhiyun #define FLT_UPDATE BIT(5) 88*4882a593Smuzhiyun /* FLT Registers */ 89*4882a593Smuzhiyun #define FLT_CONFIG0 0x160 90*4882a593Smuzhiyun #define FLT_CONFIG1 0x164 91*4882a593Smuzhiyun #define FLT_CONFIG2 0x168 92*4882a593Smuzhiyun #define FLT_CONTROL0 0x170 93*4882a593Smuzhiyun /* Main Unit 2 Registers */ 94*4882a593Smuzhiyun #define MAINUNIT_STATUS0 0x180 95*4882a593Smuzhiyun /* Video Interface Registers */ 96*4882a593Smuzhiyun #define VIDEO_INTERFACE_CONFIG0 0x800 97*4882a593Smuzhiyun #define VIDEO_INTERFACE_CONFIG1 0x804 98*4882a593Smuzhiyun #define VIDEO_INTERFACE_CONFIG2 0x808 99*4882a593Smuzhiyun #define VIDEO_INTERFACE_CONTROL0 0x80c 100*4882a593Smuzhiyun #define VIDEO_INTERFACE_STATUS0 0x814 101*4882a593Smuzhiyun /* Video Packing Registers */ 102*4882a593Smuzhiyun #define VIDEO_PACKING_CONFIG0 0x81c 103*4882a593Smuzhiyun /* Audio Interface Registers */ 104*4882a593Smuzhiyun #define AUDIO_INTERFACE_CONFIG0 0x820 105*4882a593Smuzhiyun #define AUD_IF_SEL_MSK 0x3 106*4882a593Smuzhiyun #define AUD_IF_SPDIF 0x2 107*4882a593Smuzhiyun #define AUD_IF_I2S 0x1 108*4882a593Smuzhiyun #define AUD_IF_PAI 0x0 109*4882a593Smuzhiyun #define AUD_FIFO_INIT_ON_OVF_MSK BIT(2) 110*4882a593Smuzhiyun #define AUD_FIFO_INIT_ON_OVF_EN BIT(2) 111*4882a593Smuzhiyun #define I2S_LINES_EN_MSK GENMASK(7, 4) 112*4882a593Smuzhiyun #define I2S_LINES_EN(x) BIT(x + 4) 113*4882a593Smuzhiyun #define I2S_BPCUV_RCV_MSK BIT(12) 114*4882a593Smuzhiyun #define I2S_BPCUV_RCV_EN BIT(12) 115*4882a593Smuzhiyun #define I2S_BPCUV_RCV_DIS 0 116*4882a593Smuzhiyun #define SPDIF_LINES_EN GENMASK(19, 16) 117*4882a593Smuzhiyun #define AUD_FORMAT_MSK GENMASK(26, 24) 118*4882a593Smuzhiyun #define AUD_3DOBA (0x7 << 24) 119*4882a593Smuzhiyun #define AUD_3DASP (0x6 << 24) 120*4882a593Smuzhiyun #define AUD_MSOBA (0x5 << 24) 121*4882a593Smuzhiyun #define AUD_MSASP (0x4 << 24) 122*4882a593Smuzhiyun #define AUD_HBR (0x3 << 24) 123*4882a593Smuzhiyun #define AUD_DST (0x2 << 24) 124*4882a593Smuzhiyun #define AUD_OBA (0x1 << 24) 125*4882a593Smuzhiyun #define AUD_ASP (0x0 << 24) 126*4882a593Smuzhiyun #define AUDIO_INTERFACE_CONFIG1 0x824 127*4882a593Smuzhiyun #define AUDIO_INTERFACE_CONTROL0 0x82c 128*4882a593Smuzhiyun #define AUDIO_FIFO_CLR_P BIT(0) 129*4882a593Smuzhiyun #define AUDIO_INTERFACE_STATUS0 0x834 130*4882a593Smuzhiyun /* Frame Composer Registers */ 131*4882a593Smuzhiyun #define FRAME_COMPOSER_CONFIG0 0x840 132*4882a593Smuzhiyun #define FRAME_COMPOSER_CONFIG1 0x844 133*4882a593Smuzhiyun #define FRAME_COMPOSER_CONFIG2 0x848 134*4882a593Smuzhiyun #define FRAME_COMPOSER_CONFIG3 0x84c 135*4882a593Smuzhiyun #define FRAME_COMPOSER_CONFIG4 0x850 136*4882a593Smuzhiyun #define FRAME_COMPOSER_CONFIG5 0x854 137*4882a593Smuzhiyun #define FRAME_COMPOSER_CONFIG6 0x858 138*4882a593Smuzhiyun #define FRAME_COMPOSER_CONFIG7 0x85c 139*4882a593Smuzhiyun #define FRAME_COMPOSER_CONFIG8 0x860 140*4882a593Smuzhiyun #define FRAME_COMPOSER_CONFIG9 0x864 141*4882a593Smuzhiyun #define KEEPOUT_REKEY_CFG GENMASK(9, 8) 142*4882a593Smuzhiyun #define KEEPOUT_REKEY_ALWAYS 0x2 143*4882a593Smuzhiyun #define FRAME_COMPOSER_CONTROL0 0x86c 144*4882a593Smuzhiyun /* Video Monitor Registers */ 145*4882a593Smuzhiyun #define VIDEO_MONITOR_CONFIG0 0x880 146*4882a593Smuzhiyun #define VIDEO_MONITOR_STATUS0 0x884 147*4882a593Smuzhiyun #define VIDEO_MONITOR_STATUS1 0x888 148*4882a593Smuzhiyun #define VIDEO_MONITOR_STATUS2 0x88c 149*4882a593Smuzhiyun #define VIDEO_MONITOR_STATUS3 0x890 150*4882a593Smuzhiyun #define VIDEO_MONITOR_STATUS4 0x894 151*4882a593Smuzhiyun #define VIDEO_MONITOR_STATUS5 0x898 152*4882a593Smuzhiyun #define VIDEO_MONITOR_STATUS6 0x89c 153*4882a593Smuzhiyun /* HDCP2 Logic Registers */ 154*4882a593Smuzhiyun #define HDCP2LOGIC_CONFIG0 0x8e0 155*4882a593Smuzhiyun #define HDCP2_BYPASS BIT(0) 156*4882a593Smuzhiyun #define HDCP2LOGIC_ESM_GPIO_IN 0x8e4 157*4882a593Smuzhiyun #define HDCP2LOGIC_ESM_GPIO_OUT 0x8e8 158*4882a593Smuzhiyun /* HDCP14 Registers */ 159*4882a593Smuzhiyun #define HDCP14_CONFIG0 0x900 160*4882a593Smuzhiyun #define HDCP14_CONFIG1 0x904 161*4882a593Smuzhiyun #define HDCP14_CONFIG2 0x908 162*4882a593Smuzhiyun #define HDCP14_CONFIG3 0x90c 163*4882a593Smuzhiyun #define HDCP14_KEY_SEED 0x914 164*4882a593Smuzhiyun #define HDCP14_KEY_H 0x918 165*4882a593Smuzhiyun #define HDCP14_KEY_L 0x91c 166*4882a593Smuzhiyun #define HDCP14_KEY_STATUS 0x920 167*4882a593Smuzhiyun #define HDCP14_AKSV_H 0x924 168*4882a593Smuzhiyun #define HDCP14_AKSV_L 0x928 169*4882a593Smuzhiyun #define HDCP14_AN_H 0x92c 170*4882a593Smuzhiyun #define HDCP14_AN_L 0x930 171*4882a593Smuzhiyun #define HDCP14_STATUS0 0x934 172*4882a593Smuzhiyun #define HDCP14_STATUS1 0x938 173*4882a593Smuzhiyun /* Scrambler Registers */ 174*4882a593Smuzhiyun #define SCRAMB_CONFIG0 0x960 175*4882a593Smuzhiyun /* Video Configuration Registers */ 176*4882a593Smuzhiyun #define LINK_CONFIG0 0x968 177*4882a593Smuzhiyun #define OPMODE_FRL_4LANES BIT(8) 178*4882a593Smuzhiyun #define OPMODE_DVI BIT(4) 179*4882a593Smuzhiyun #define OPMODE_FRL BIT(0) 180*4882a593Smuzhiyun /* TMDS FIFO Registers */ 181*4882a593Smuzhiyun #define TMDS_FIFO_CONFIG0 0x970 182*4882a593Smuzhiyun #define TMDS_FIFO_CONTROL0 0x974 183*4882a593Smuzhiyun /* FRL RSFEC Registers */ 184*4882a593Smuzhiyun #define FRL_RSFEC_CONFIG0 0xa20 185*4882a593Smuzhiyun #define FRL_RSFEC_STATUS0 0xa30 186*4882a593Smuzhiyun /* FRL Packetizer Registers */ 187*4882a593Smuzhiyun #define FRL_PKTZ_CONFIG0 0xa40 188*4882a593Smuzhiyun #define FRL_PKTZ_CONTROL0 0xa44 189*4882a593Smuzhiyun #define FRL_PKTZ_CONTROL1 0xa50 190*4882a593Smuzhiyun #define FRL_PKTZ_STATUS1 0xa54 191*4882a593Smuzhiyun /* Packet Scheduler Registers */ 192*4882a593Smuzhiyun #define PKTSCHED_CONFIG0 0xa80 193*4882a593Smuzhiyun #define PKTSCHED_PRQUEUE0_CONFIG0 0xa84 194*4882a593Smuzhiyun #define PKTSCHED_PRQUEUE1_CONFIG0 0xa88 195*4882a593Smuzhiyun #define PKTSCHED_PRQUEUE2_CONFIG0 0xa8c 196*4882a593Smuzhiyun #define PKTSCHED_PRQUEUE2_CONFIG1 0xa90 197*4882a593Smuzhiyun #define PKTSCHED_PRQUEUE2_CONFIG2 0xa94 198*4882a593Smuzhiyun #define PKTSCHED_PKT_CONFIG0 0xa98 199*4882a593Smuzhiyun #define PKTSCHED_PKT_CONFIG1 0xa9c 200*4882a593Smuzhiyun #define PKTSCHED_VSI_FIELDRATE BIT(14) 201*4882a593Smuzhiyun #define PKTSCHED_DRMI_FIELDRATE BIT(13) 202*4882a593Smuzhiyun #define PKTSCHED_AVI_FIELDRATE BIT(12) 203*4882a593Smuzhiyun #define PKTSCHED_PKT_CONFIG2 0xaa0 204*4882a593Smuzhiyun #define PKTSCHED_PKT_CONFIG3 0xaa4 205*4882a593Smuzhiyun #define PKTSCHED_PKT_EN 0xaa8 206*4882a593Smuzhiyun #define PKTSCHED_DRMI_TX_EN BIT(17) 207*4882a593Smuzhiyun #define PKTSCHED_AUDI_TX_EN BIT(15) 208*4882a593Smuzhiyun #define PKTSCHED_AVI_TX_EN BIT(13) 209*4882a593Smuzhiyun #define PKTSCHED_VSI_TX_EN BIT(12) 210*4882a593Smuzhiyun #define PKTSCHED_EMP_CVTEM_TX_EN BIT(10) 211*4882a593Smuzhiyun #define PKTSCHED_AMD_TX_EN BIT(8) 212*4882a593Smuzhiyun #define PKTSCHED_GCP_TX_EN BIT(3) 213*4882a593Smuzhiyun #define PKTSCHED_AUDS_TX_EN BIT(2) 214*4882a593Smuzhiyun #define PKTSCHED_ACR_TX_EN BIT(1) 215*4882a593Smuzhiyun #define PKTSCHED_NULL_TX_EN BIT(0) 216*4882a593Smuzhiyun #define PKTSCHED_PKT_CONTROL0 0xaac 217*4882a593Smuzhiyun #define PKTSCHED_PKT_SEND 0xab0 218*4882a593Smuzhiyun #define PKTSCHED_PKT_STATUS0 0xab4 219*4882a593Smuzhiyun #define PKTSCHED_PKT_STATUS1 0xab8 220*4882a593Smuzhiyun #define PKT_NULL_CONTENTS0 0xb00 221*4882a593Smuzhiyun #define PKT_NULL_CONTENTS1 0xb04 222*4882a593Smuzhiyun #define PKT_NULL_CONTENTS2 0xb08 223*4882a593Smuzhiyun #define PKT_NULL_CONTENTS3 0xb0c 224*4882a593Smuzhiyun #define PKT_NULL_CONTENTS4 0xb10 225*4882a593Smuzhiyun #define PKT_NULL_CONTENTS5 0xb14 226*4882a593Smuzhiyun #define PKT_NULL_CONTENTS6 0xb18 227*4882a593Smuzhiyun #define PKT_NULL_CONTENTS7 0xb1c 228*4882a593Smuzhiyun #define PKT_ACP_CONTENTS0 0xb20 229*4882a593Smuzhiyun #define PKT_ACP_CONTENTS1 0xb24 230*4882a593Smuzhiyun #define PKT_ACP_CONTENTS2 0xb28 231*4882a593Smuzhiyun #define PKT_ACP_CONTENTS3 0xb2c 232*4882a593Smuzhiyun #define PKT_ACP_CONTENTS4 0xb30 233*4882a593Smuzhiyun #define PKT_ACP_CONTENTS5 0xb34 234*4882a593Smuzhiyun #define PKT_ACP_CONTENTS6 0xb38 235*4882a593Smuzhiyun #define PKT_ACP_CONTENTS7 0xb3c 236*4882a593Smuzhiyun #define PKT_ISRC1_CONTENTS0 0xb40 237*4882a593Smuzhiyun #define PKT_ISRC1_CONTENTS1 0xb44 238*4882a593Smuzhiyun #define PKT_ISRC1_CONTENTS2 0xb48 239*4882a593Smuzhiyun #define PKT_ISRC1_CONTENTS3 0xb4c 240*4882a593Smuzhiyun #define PKT_ISRC1_CONTENTS4 0xb50 241*4882a593Smuzhiyun #define PKT_ISRC1_CONTENTS5 0xb54 242*4882a593Smuzhiyun #define PKT_ISRC1_CONTENTS6 0xb58 243*4882a593Smuzhiyun #define PKT_ISRC1_CONTENTS7 0xb5c 244*4882a593Smuzhiyun #define PKT_ISRC2_CONTENTS0 0xb60 245*4882a593Smuzhiyun #define PKT_ISRC2_CONTENTS1 0xb64 246*4882a593Smuzhiyun #define PKT_ISRC2_CONTENTS2 0xb68 247*4882a593Smuzhiyun #define PKT_ISRC2_CONTENTS3 0xb6c 248*4882a593Smuzhiyun #define PKT_ISRC2_CONTENTS4 0xb70 249*4882a593Smuzhiyun #define PKT_ISRC2_CONTENTS5 0xb74 250*4882a593Smuzhiyun #define PKT_ISRC2_CONTENTS6 0xb78 251*4882a593Smuzhiyun #define PKT_ISRC2_CONTENTS7 0xb7c 252*4882a593Smuzhiyun #define PKT_GMD_CONTENTS0 0xb80 253*4882a593Smuzhiyun #define PKT_GMD_CONTENTS1 0xb84 254*4882a593Smuzhiyun #define PKT_GMD_CONTENTS2 0xb88 255*4882a593Smuzhiyun #define PKT_GMD_CONTENTS3 0xb8c 256*4882a593Smuzhiyun #define PKT_GMD_CONTENTS4 0xb90 257*4882a593Smuzhiyun #define PKT_GMD_CONTENTS5 0xb94 258*4882a593Smuzhiyun #define PKT_GMD_CONTENTS6 0xb98 259*4882a593Smuzhiyun #define PKT_GMD_CONTENTS7 0xb9c 260*4882a593Smuzhiyun #define PKT_AMD_CONTENTS0 0xba0 261*4882a593Smuzhiyun #define PKT_AMD_CONTENTS1 0xba4 262*4882a593Smuzhiyun #define PKT_AMD_CONTENTS2 0xba8 263*4882a593Smuzhiyun #define PKT_AMD_CONTENTS3 0xbac 264*4882a593Smuzhiyun #define PKT_AMD_CONTENTS4 0xbb0 265*4882a593Smuzhiyun #define PKT_AMD_CONTENTS5 0xbb4 266*4882a593Smuzhiyun #define PKT_AMD_CONTENTS6 0xbb8 267*4882a593Smuzhiyun #define PKT_AMD_CONTENTS7 0xbbc 268*4882a593Smuzhiyun #define PKT_VSI_CONTENTS0 0xbc0 269*4882a593Smuzhiyun #define PKT_VSI_CONTENTS1 0xbc4 270*4882a593Smuzhiyun #define PKT_VSI_CONTENTS2 0xbc8 271*4882a593Smuzhiyun #define PKT_VSI_CONTENTS3 0xbcc 272*4882a593Smuzhiyun #define PKT_VSI_CONTENTS4 0xbd0 273*4882a593Smuzhiyun #define PKT_VSI_CONTENTS5 0xbd4 274*4882a593Smuzhiyun #define PKT_VSI_CONTENTS6 0xbd8 275*4882a593Smuzhiyun #define PKT_VSI_CONTENTS7 0xbdc 276*4882a593Smuzhiyun #define PKT_AVI_CONTENTS0 0xbe0 277*4882a593Smuzhiyun #define HDMI_FC_AVICONF0_ACTIVE_FMT_INFO_PRESENT BIT(4) 278*4882a593Smuzhiyun #define HDMI_FC_AVICONF0_BAR_DATA_VERT_BAR 0x04 279*4882a593Smuzhiyun #define HDMI_FC_AVICONF0_BAR_DATA_HORIZ_BAR 0x08 280*4882a593Smuzhiyun #define HDMI_FC_AVICONF2_IT_CONTENT_VALID 0x80 281*4882a593Smuzhiyun #define PKT_AVI_CONTENTS1 0xbe4 282*4882a593Smuzhiyun #define PKT_AVI_CONTENTS2 0xbe8 283*4882a593Smuzhiyun #define PKT_AVI_CONTENTS3 0xbec 284*4882a593Smuzhiyun #define PKT_AVI_CONTENTS4 0xbf0 285*4882a593Smuzhiyun #define PKT_AVI_CONTENTS5 0xbf4 286*4882a593Smuzhiyun #define PKT_AVI_CONTENTS6 0xbf8 287*4882a593Smuzhiyun #define PKT_AVI_CONTENTS7 0xbfc 288*4882a593Smuzhiyun #define PKT_SPDI_CONTENTS0 0xc00 289*4882a593Smuzhiyun #define PKT_SPDI_CONTENTS1 0xc04 290*4882a593Smuzhiyun #define PKT_SPDI_CONTENTS2 0xc08 291*4882a593Smuzhiyun #define PKT_SPDI_CONTENTS3 0xc0c 292*4882a593Smuzhiyun #define PKT_SPDI_CONTENTS4 0xc10 293*4882a593Smuzhiyun #define PKT_SPDI_CONTENTS5 0xc14 294*4882a593Smuzhiyun #define PKT_SPDI_CONTENTS6 0xc18 295*4882a593Smuzhiyun #define PKT_SPDI_CONTENTS7 0xc1c 296*4882a593Smuzhiyun #define PKT_AUDI_CONTENTS0 0xc20 297*4882a593Smuzhiyun #define PKT_AUDI_CONTENTS1 0xc24 298*4882a593Smuzhiyun #define PKT_AUDI_CONTENTS2 0xc28 299*4882a593Smuzhiyun #define PKT_AUDI_CONTENTS3 0xc2c 300*4882a593Smuzhiyun #define PKT_AUDI_CONTENTS4 0xc30 301*4882a593Smuzhiyun #define PKT_AUDI_CONTENTS5 0xc34 302*4882a593Smuzhiyun #define PKT_AUDI_CONTENTS6 0xc38 303*4882a593Smuzhiyun #define PKT_AUDI_CONTENTS7 0xc3c 304*4882a593Smuzhiyun #define PKT_NVI_CONTENTS0 0xc40 305*4882a593Smuzhiyun #define PKT_NVI_CONTENTS1 0xc44 306*4882a593Smuzhiyun #define PKT_NVI_CONTENTS2 0xc48 307*4882a593Smuzhiyun #define PKT_NVI_CONTENTS3 0xc4c 308*4882a593Smuzhiyun #define PKT_NVI_CONTENTS4 0xc50 309*4882a593Smuzhiyun #define PKT_NVI_CONTENTS5 0xc54 310*4882a593Smuzhiyun #define PKT_NVI_CONTENTS6 0xc58 311*4882a593Smuzhiyun #define PKT_NVI_CONTENTS7 0xc5c 312*4882a593Smuzhiyun #define PKT_DRMI_CONTENTS0 0xc60 313*4882a593Smuzhiyun #define PKT_DRMI_CONTENTS1 0xc64 314*4882a593Smuzhiyun #define PKT_DRMI_CONTENTS2 0xc68 315*4882a593Smuzhiyun #define PKT_DRMI_CONTENTS3 0xc6c 316*4882a593Smuzhiyun #define PKT_DRMI_CONTENTS4 0xc70 317*4882a593Smuzhiyun #define PKT_DRMI_CONTENTS5 0xc74 318*4882a593Smuzhiyun #define PKT_DRMI_CONTENTS6 0xc78 319*4882a593Smuzhiyun #define PKT_DRMI_CONTENTS7 0xc7c 320*4882a593Smuzhiyun #define PKT_GHDMI1_CONTENTS0 0xc80 321*4882a593Smuzhiyun #define PKT_GHDMI1_CONTENTS1 0xc84 322*4882a593Smuzhiyun #define PKT_GHDMI1_CONTENTS2 0xc88 323*4882a593Smuzhiyun #define PKT_GHDMI1_CONTENTS3 0xc8c 324*4882a593Smuzhiyun #define PKT_GHDMI1_CONTENTS4 0xc90 325*4882a593Smuzhiyun #define PKT_GHDMI1_CONTENTS5 0xc94 326*4882a593Smuzhiyun #define PKT_GHDMI1_CONTENTS6 0xc98 327*4882a593Smuzhiyun #define PKT_GHDMI1_CONTENTS7 0xc9c 328*4882a593Smuzhiyun #define PKT_GHDMI2_CONTENTS0 0xca0 329*4882a593Smuzhiyun #define PKT_GHDMI2_CONTENTS1 0xca4 330*4882a593Smuzhiyun #define PKT_GHDMI2_CONTENTS2 0xca8 331*4882a593Smuzhiyun #define PKT_GHDMI2_CONTENTS3 0xcac 332*4882a593Smuzhiyun #define PKT_GHDMI2_CONTENTS4 0xcb0 333*4882a593Smuzhiyun #define PKT_GHDMI2_CONTENTS5 0xcb4 334*4882a593Smuzhiyun #define PKT_GHDMI2_CONTENTS6 0xcb8 335*4882a593Smuzhiyun #define PKT_GHDMI2_CONTENTS7 0xcbc 336*4882a593Smuzhiyun /* EMP Packetizer Registers */ 337*4882a593Smuzhiyun #define PKT_EMP_CONFIG0 0xce0 338*4882a593Smuzhiyun #define PKT_EMP_CONTROL0 0xcec 339*4882a593Smuzhiyun #define PKT_EMP_CONTROL1 0xcf0 340*4882a593Smuzhiyun #define PKT_EMP_CONTROL2 0xcf4 341*4882a593Smuzhiyun #define PKT_EMP_VTEM_CONTENTS0 0xd00 342*4882a593Smuzhiyun #define PKT_EMP_VTEM_CONTENTS1 0xd04 343*4882a593Smuzhiyun #define PKT_EMP_VTEM_CONTENTS2 0xd08 344*4882a593Smuzhiyun #define PKT_EMP_VTEM_CONTENTS3 0xd0c 345*4882a593Smuzhiyun #define PKT_EMP_VTEM_CONTENTS4 0xd10 346*4882a593Smuzhiyun #define PKT_EMP_VTEM_CONTENTS5 0xd14 347*4882a593Smuzhiyun #define PKT_EMP_VTEM_CONTENTS6 0xd18 348*4882a593Smuzhiyun #define PKT_EMP_VTEM_CONTENTS7 0xd1c 349*4882a593Smuzhiyun #define PKT0_EMP_CVTEM_CONTENTS0 0xd20 350*4882a593Smuzhiyun #define PKT0_EMP_CVTEM_CONTENTS1 0xd24 351*4882a593Smuzhiyun #define PKT0_EMP_CVTEM_CONTENTS2 0xd28 352*4882a593Smuzhiyun #define PKT0_EMP_CVTEM_CONTENTS3 0xd2c 353*4882a593Smuzhiyun #define PKT0_EMP_CVTEM_CONTENTS4 0xd30 354*4882a593Smuzhiyun #define PKT0_EMP_CVTEM_CONTENTS5 0xd34 355*4882a593Smuzhiyun #define PKT0_EMP_CVTEM_CONTENTS6 0xd38 356*4882a593Smuzhiyun #define PKT0_EMP_CVTEM_CONTENTS7 0xd3c 357*4882a593Smuzhiyun #define PKT1_EMP_CVTEM_CONTENTS0 0xd40 358*4882a593Smuzhiyun #define PKT1_EMP_CVTEM_CONTENTS1 0xd44 359*4882a593Smuzhiyun #define PKT1_EMP_CVTEM_CONTENTS2 0xd48 360*4882a593Smuzhiyun #define PKT1_EMP_CVTEM_CONTENTS3 0xd4c 361*4882a593Smuzhiyun #define PKT1_EMP_CVTEM_CONTENTS4 0xd50 362*4882a593Smuzhiyun #define PKT1_EMP_CVTEM_CONTENTS5 0xd54 363*4882a593Smuzhiyun #define PKT1_EMP_CVTEM_CONTENTS6 0xd58 364*4882a593Smuzhiyun #define PKT1_EMP_CVTEM_CONTENTS7 0xd5c 365*4882a593Smuzhiyun #define PKT2_EMP_CVTEM_CONTENTS0 0xd60 366*4882a593Smuzhiyun #define PKT2_EMP_CVTEM_CONTENTS1 0xd64 367*4882a593Smuzhiyun #define PKT2_EMP_CVTEM_CONTENTS2 0xd68 368*4882a593Smuzhiyun #define PKT2_EMP_CVTEM_CONTENTS3 0xd6c 369*4882a593Smuzhiyun #define PKT2_EMP_CVTEM_CONTENTS4 0xd70 370*4882a593Smuzhiyun #define PKT2_EMP_CVTEM_CONTENTS5 0xd74 371*4882a593Smuzhiyun #define PKT2_EMP_CVTEM_CONTENTS6 0xd78 372*4882a593Smuzhiyun #define PKT2_EMP_CVTEM_CONTENTS7 0xd7c 373*4882a593Smuzhiyun #define PKT3_EMP_CVTEM_CONTENTS0 0xd80 374*4882a593Smuzhiyun #define PKT3_EMP_CVTEM_CONTENTS1 0xd84 375*4882a593Smuzhiyun #define PKT3_EMP_CVTEM_CONTENTS2 0xd88 376*4882a593Smuzhiyun #define PKT3_EMP_CVTEM_CONTENTS3 0xd8c 377*4882a593Smuzhiyun #define PKT3_EMP_CVTEM_CONTENTS4 0xd90 378*4882a593Smuzhiyun #define PKT3_EMP_CVTEM_CONTENTS5 0xd94 379*4882a593Smuzhiyun #define PKT3_EMP_CVTEM_CONTENTS6 0xd98 380*4882a593Smuzhiyun #define PKT3_EMP_CVTEM_CONTENTS7 0xd9c 381*4882a593Smuzhiyun #define PKT4_EMP_CVTEM_CONTENTS0 0xda0 382*4882a593Smuzhiyun #define PKT4_EMP_CVTEM_CONTENTS1 0xda4 383*4882a593Smuzhiyun #define PKT4_EMP_CVTEM_CONTENTS2 0xda8 384*4882a593Smuzhiyun #define PKT4_EMP_CVTEM_CONTENTS3 0xdac 385*4882a593Smuzhiyun #define PKT4_EMP_CVTEM_CONTENTS4 0xdb0 386*4882a593Smuzhiyun #define PKT4_EMP_CVTEM_CONTENTS5 0xdb4 387*4882a593Smuzhiyun #define PKT4_EMP_CVTEM_CONTENTS6 0xdb8 388*4882a593Smuzhiyun #define PKT4_EMP_CVTEM_CONTENTS7 0xdbc 389*4882a593Smuzhiyun #define PKT5_EMP_CVTEM_CONTENTS0 0xdc0 390*4882a593Smuzhiyun #define PKT5_EMP_CVTEM_CONTENTS1 0xdc4 391*4882a593Smuzhiyun #define PKT5_EMP_CVTEM_CONTENTS2 0xdc8 392*4882a593Smuzhiyun #define PKT5_EMP_CVTEM_CONTENTS3 0xdcc 393*4882a593Smuzhiyun #define PKT5_EMP_CVTEM_CONTENTS4 0xdd0 394*4882a593Smuzhiyun #define PKT5_EMP_CVTEM_CONTENTS5 0xdd4 395*4882a593Smuzhiyun #define PKT5_EMP_CVTEM_CONTENTS6 0xdd8 396*4882a593Smuzhiyun #define PKT5_EMP_CVTEM_CONTENTS7 0xddc 397*4882a593Smuzhiyun /* Audio Packetizer Registers */ 398*4882a593Smuzhiyun #define AUDPKT_CONTROL0 0xe20 399*4882a593Smuzhiyun #define AUDPKT_PBIT_FORCE_EN_MASK BIT(12) 400*4882a593Smuzhiyun #define AUDPKT_PBIT_FORCE_EN BIT(12) 401*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR_EN_MASK BIT(0) 402*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR_EN BIT(0) 403*4882a593Smuzhiyun #define AUDPKT_CONTROL1 0xe24 404*4882a593Smuzhiyun #define AUDPKT_ACR_CONTROL0 0xe40 405*4882a593Smuzhiyun #define AUDPKT_ACR_N_VALUE 0xfffff 406*4882a593Smuzhiyun #define AUDPKT_ACR_CONTROL1 0xe44 407*4882a593Smuzhiyun #define AUDPKT_ACR_CTS_OVR_VAL_MSK GENMASK(23, 4) 408*4882a593Smuzhiyun #define AUDPKT_ACR_CTS_OVR_VAL(x) ((x) << 4) 409*4882a593Smuzhiyun #define AUDPKT_ACR_CTS_OVR_EN_MSK BIT(1) 410*4882a593Smuzhiyun #define AUDPKT_ACR_CTS_OVR_EN BIT(1) 411*4882a593Smuzhiyun #define AUDPKT_ACR_STATUS0 0xe4c 412*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR0 0xe60 413*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR1 0xe64 414*4882a593Smuzhiyun /* IEC60958 Byte 3: Sampleing frenuency Bits 24 to 27 */ 415*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_SR_MASK GENMASK(3, 0) 416*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_SR_22050 0x4 417*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_SR_24000 0x6 418*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_SR_32000 0x3 419*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_SR_44100 0x0 420*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_SR_48000 0x2 421*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_SR_88200 0x8 422*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_SR_96000 0xa 423*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_SR_176400 0xc 424*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_SR_192000 0xe 425*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_SR_768000 0x9 426*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_SR_NOT_INDICATED 0x1 427*4882a593Smuzhiyun /* IEC60958 Byte 4: Original Sampleing frenuency Bits 36 to 39 */ 428*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_0SR_MASK GENMASK(15, 12) 429*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_8000 0x6 430*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_11025 0xa 431*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_12000 0x2 432*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_16000 0x8 433*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_22050 0xb 434*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_24000 0x9 435*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_32000 0xc 436*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_44100 0xf 437*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_48000 0xd 438*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_88200 0x7 439*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_96000 0x5 440*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_176400 0x3 441*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_192000 0x1 442*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OSR_NOT_INDICATED 0x0 443*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR2 0xe68 444*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR3 0xe6c 445*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR4 0xe70 446*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR5 0xe74 447*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR6 0xe78 448*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR7 0xe7c 449*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR8 0xe80 450*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR9 0xe84 451*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR10 0xe88 452*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR11 0xe8c 453*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR12 0xe90 454*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR13 0xe94 455*4882a593Smuzhiyun #define AUDPKT_CHSTATUS_OVR14 0xe98 456*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC0 0xea0 457*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC1 0xea4 458*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC2 0xea8 459*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC3 0xeac 460*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC4 0xeb0 461*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC5 0xeb4 462*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC6 0xeb8 463*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC7 0xebc 464*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC8 0xec0 465*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC9 0xec4 466*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC10 0xec8 467*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC11 0xecc 468*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC12 0xed0 469*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC13 0xed4 470*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC14 0xed8 471*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC15 0xedc 472*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC16 0xee0 473*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC17 0xee4 474*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC18 0xee8 475*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC19 0xeec 476*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC20 0xef0 477*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC21 0xef4 478*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC22 0xef8 479*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC23 0xefc 480*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC24 0xf00 481*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC25 0xf04 482*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC26 0xf08 483*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC27 0xf0c 484*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC28 0xf10 485*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC29 0xf14 486*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC30 0xf18 487*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC31 0xf1c 488*4882a593Smuzhiyun #define AUDPKT_USRDATA_OVR_MSG_GENERIC32 0xf20 489*4882a593Smuzhiyun #define AUDPKT_VBIT_OVR0 0xf24 490*4882a593Smuzhiyun /* CEC Registers */ 491*4882a593Smuzhiyun #define CEC_TX_CONTROL 0x1000 492*4882a593Smuzhiyun #define CEC_STATUS 0x1004 493*4882a593Smuzhiyun #define CEC_CONFIG 0x1008 494*4882a593Smuzhiyun #define CEC_ADDR 0x100c 495*4882a593Smuzhiyun #define CEC_TX_COUNT 0x1020 496*4882a593Smuzhiyun #define CEC_TX_DATA3_0 0x1024 497*4882a593Smuzhiyun #define CEC_TX_DATA7_4 0x1028 498*4882a593Smuzhiyun #define CEC_TX_DATA11_8 0x102c 499*4882a593Smuzhiyun #define CEC_TX_DATA15_12 0x1030 500*4882a593Smuzhiyun #define CEC_RX_COUNT_STATUS 0x1040 501*4882a593Smuzhiyun #define CEC_RX_DATA3_0 0x1044 502*4882a593Smuzhiyun #define CEC_RX_DATA7_4 0x1048 503*4882a593Smuzhiyun #define CEC_RX_DATA11_8 0x104c 504*4882a593Smuzhiyun #define CEC_RX_DATA15_12 0x1050 505*4882a593Smuzhiyun #define CEC_LOCK_CONTROL 0x1054 506*4882a593Smuzhiyun #define CEC_RXQUAL_BITTIME_CONFIG 0x1060 507*4882a593Smuzhiyun #define CEC_RX_BITTIME_CONFIG 0x1064 508*4882a593Smuzhiyun #define CEC_TX_BITTIME_CONFIG 0x1068 509*4882a593Smuzhiyun /* eARC RX CMDC Registers */ 510*4882a593Smuzhiyun #define EARCRX_CMDC_CONFIG0 0x1800 511*4882a593Smuzhiyun #define EARCRX_XACTREAD_STOP_CFG BIT(26) 512*4882a593Smuzhiyun #define EARCRX_XACTREAD_RETRY_CFG BIT(25) 513*4882a593Smuzhiyun #define EARCRX_CMDC_DSCVR_EARCVALID0_TO_DISC1 BIT(24) 514*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RESTART_EN BIT(18) 515*4882a593Smuzhiyun #define EARCRX_CMDC_CONFIG1 0x1804 516*4882a593Smuzhiyun #define EARCRX_CMDC_CONTROL 0x1808 517*4882a593Smuzhiyun #define EARCRX_CMDC_HEARTBEAT_LOSS_EN BIT(4) 518*4882a593Smuzhiyun #define EARCRX_CMDC_DISCOVERY_EN BIT(3) 519*4882a593Smuzhiyun #define EARCRX_CONNECTOR_HPD BIT(1) 520*4882a593Smuzhiyun #define EARCRX_CMDC_WHITELIST0_CONFIG 0x180c 521*4882a593Smuzhiyun #define EARCRX_CMDC_WHITELIST1_CONFIG 0x1810 522*4882a593Smuzhiyun #define EARCRX_CMDC_WHITELIST2_CONFIG 0x1814 523*4882a593Smuzhiyun #define EARCRX_CMDC_WHITELIST3_CONFIG 0x1818 524*4882a593Smuzhiyun #define EARCRX_CMDC_STATUS 0x181c 525*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_INFO 0x1820 526*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_ACTION 0x1824 527*4882a593Smuzhiyun #define EARCRX_CMDC_HEARTBEAT_RXSTAT_SE 0x1828 528*4882a593Smuzhiyun #define EARCRX_CMDC_HEARTBEAT_STATUS 0x182c 529*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR0 0x1840 530*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR1 0x1844 531*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR2 0x1848 532*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR3 0x184c 533*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR4 0x1850 534*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR5 0x1854 535*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR6 0x1858 536*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR7 0x185c 537*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR8 0x1860 538*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR9 0x1864 539*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR10 0x1868 540*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR11 0x186c 541*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR12 0x1870 542*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR13 0x1874 543*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR14 0x1878 544*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR15 0x187c 545*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR16 0x1880 546*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR17 0x1884 547*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR18 0x1888 548*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR19 0x188c 549*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR20 0x1890 550*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR21 0x1894 551*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR22 0x1898 552*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR23 0x189c 553*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR24 0x18a0 554*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR25 0x18a4 555*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR26 0x18a8 556*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR27 0x18ac 557*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR28 0x18b0 558*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR29 0x18b4 559*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR30 0x18b8 560*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR31 0x18bc 561*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR32 0x18c0 562*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR33 0x18c4 563*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR34 0x18c8 564*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR35 0x18cc 565*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR36 0x18d0 566*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR37 0x18d4 567*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR38 0x18d8 568*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR39 0x18dc 569*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR40 0x18e0 570*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR41 0x18e4 571*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR42 0x18e8 572*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR43 0x18ec 573*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR44 0x18f0 574*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR45 0x18f4 575*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR46 0x18f8 576*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR47 0x18fc 577*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR48 0x1900 578*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR49 0x1904 579*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR50 0x1908 580*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR51 0x190c 581*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR52 0x1910 582*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR53 0x1914 583*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR54 0x1918 584*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR55 0x191c 585*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR56 0x1920 586*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR57 0x1924 587*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR58 0x1928 588*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR59 0x192c 589*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR60 0x1930 590*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR61 0x1934 591*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR62 0x1938 592*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR63 0x193c 593*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_WR64 0x1940 594*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD0 0x1960 595*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD1 0x1964 596*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD2 0x1968 597*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD3 0x196c 598*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD4 0x1970 599*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD5 0x1974 600*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD6 0x1978 601*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD7 0x197c 602*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD8 0x1980 603*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD9 0x1984 604*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD10 0x1988 605*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD11 0x198c 606*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD12 0x1990 607*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD13 0x1994 608*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD14 0x1998 609*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD15 0x199c 610*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD16 0x19a0 611*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD17 0x19a4 612*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD18 0x19a8 613*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD19 0x19ac 614*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD20 0x19b0 615*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD21 0x19b4 616*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD22 0x19b8 617*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD23 0x19bc 618*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD24 0x19c0 619*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD25 0x19c4 620*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD26 0x19c8 621*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD27 0x19cc 622*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD28 0x19d0 623*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD29 0x19d4 624*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD30 0x19d8 625*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD31 0x19dc 626*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD32 0x19e0 627*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD33 0x19e4 628*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD34 0x19e8 629*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD35 0x19ec 630*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD36 0x19f0 631*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD37 0x19f4 632*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD38 0x19f8 633*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD39 0x19fc 634*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD40 0x1a00 635*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD41 0x1a04 636*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD42 0x1a08 637*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD43 0x1a0c 638*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD44 0x1a10 639*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD45 0x1a14 640*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD46 0x1a18 641*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD47 0x1a1c 642*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD48 0x1a20 643*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD49 0x1a24 644*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD50 0x1a28 645*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD51 0x1a2c 646*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD52 0x1a30 647*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD53 0x1a34 648*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD54 0x1a38 649*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD55 0x1a3c 650*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD56 0x1a40 651*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD57 0x1a44 652*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD58 0x1a48 653*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD59 0x1a4c 654*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD60 0x1a50 655*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD61 0x1a54 656*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD62 0x1a58 657*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD63 0x1a5c 658*4882a593Smuzhiyun #define EARCRX_CMDC_XACT_RD64 0x1a60 659*4882a593Smuzhiyun #define EARCRX_CMDC_SYNC_CONFIG 0x1b00 660*4882a593Smuzhiyun /* eARC RX DMAC Registers */ 661*4882a593Smuzhiyun #define EARCRX_DMAC_PHY_CONTROL 0x1c00 662*4882a593Smuzhiyun #define EARCRX_DMAC_CONFIG 0x1c08 663*4882a593Smuzhiyun #define EARCRX_DMAC_CONTROL0 0x1c0c 664*4882a593Smuzhiyun #define EARCRX_DMAC_AUDIO_EN BIT(1) 665*4882a593Smuzhiyun #define EARCRX_DMAC_EN BIT(0) 666*4882a593Smuzhiyun #define EARCRX_DMAC_CONTROL1 0x1c10 667*4882a593Smuzhiyun #define EARCRX_DMAC_STATUS 0x1c14 668*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS0 0x1c18 669*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS1 0x1c1c 670*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS2 0x1c20 671*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS3 0x1c24 672*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS4 0x1c28 673*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS5 0x1c2c 674*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC0 0x1c30 675*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC1 0x1c34 676*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC2 0x1c38 677*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC3 0x1c3c 678*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC4 0x1c40 679*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC5 0x1c44 680*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC6 0x1c48 681*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC7 0x1c4c 682*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC8 0x1c50 683*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC9 0x1c54 684*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC10 0x1c58 685*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_AC11 0x1c5c 686*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT0 0x1c60 687*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT1 0x1c64 688*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT2 0x1c68 689*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT3 0x1c6c 690*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT4 0x1c70 691*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT5 0x1c74 692*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT6 0x1c78 693*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT7 0x1c7c 694*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT8 0x1c80 695*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT9 0x1c84 696*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT10 0x1c88 697*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC1_PKT11 0x1c8c 698*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT0 0x1c90 699*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT1 0x1c94 700*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT2 0x1c98 701*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT3 0x1c9c 702*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT4 0x1ca0 703*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT5 0x1ca4 704*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT6 0x1ca8 705*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT7 0x1cac 706*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT8 0x1cb0 707*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT9 0x1cb4 708*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT10 0x1cb8 709*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_HDMI_ISRC2_PKT11 0x1cbc 710*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC0 0x1cc0 711*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC1 0x1cc4 712*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC2 0x1cc8 713*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC3 0x1ccc 714*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC4 0x1cd0 715*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC5 0x1cd4 716*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC6 0x1cd8 717*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC7 0x1cdc 718*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC8 0x1ce0 719*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC9 0x1ce4 720*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC10 0x1ce8 721*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC11 0x1cec 722*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC12 0x1cf0 723*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC13 0x1cf4 724*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC14 0x1cf8 725*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC15 0x1cfc 726*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC16 0x1d00 727*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC17 0x1d04 728*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC18 0x1d08 729*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC19 0x1d0c 730*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC20 0x1d10 731*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC21 0x1d14 732*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC22 0x1d18 733*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC23 0x1d1c 734*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC24 0x1d20 735*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC25 0x1d24 736*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC26 0x1d28 737*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC27 0x1d2c 738*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC28 0x1d30 739*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC29 0x1d34 740*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC30 0x1d38 741*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC31 0x1d3c 742*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_MSG_GENERIC32 0x1d40 743*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER0 0x1d44 744*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER1 0x1d48 745*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER2 0x1d4c 746*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER3 0x1d50 747*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER4 0x1d54 748*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER5 0x1d58 749*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER6 0x1d5c 750*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER7 0x1d60 751*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER8 0x1d64 752*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER9 0x1d68 753*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER10 0x1d6c 754*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER11 0x1d70 755*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER12 0x1d74 756*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER13 0x1d78 757*4882a593Smuzhiyun #define EARCRX_DMAC_CHSTATUS_STREAMER14 0x1d7c 758*4882a593Smuzhiyun #define EARCRX_DMAC_USRDATA_STREAMER0 0x1d80 759*4882a593Smuzhiyun /* Main Unit Interrupt Registers */ 760*4882a593Smuzhiyun #define MAIN_INTVEC_INDEX 0x3000 761*4882a593Smuzhiyun #define MAINUNIT_0_INT_STATUS 0x3010 762*4882a593Smuzhiyun #define MAINUNIT_0_INT_MASK_N 0x3014 763*4882a593Smuzhiyun #define MAINUNIT_0_INT_CLEAR 0x3018 764*4882a593Smuzhiyun #define MAINUNIT_0_INT_FORCE 0x301c 765*4882a593Smuzhiyun #define MAINUNIT_1_INT_STATUS 0x3020 766*4882a593Smuzhiyun #define FLT_EXIT_TO_LTSL_IRQ BIT(22) 767*4882a593Smuzhiyun #define FLT_EXIT_TO_LTS4_IRQ BIT(21) 768*4882a593Smuzhiyun #define FLT_EXIT_TO_LTSP_IRQ BIT(20) 769*4882a593Smuzhiyun #define SCDC_NACK_RCVD_IRQ BIT(12) 770*4882a593Smuzhiyun #define SCDC_RR_REPLY_STOP_IRQ BIT(11) 771*4882a593Smuzhiyun #define SCDC_UPD_FLAGS_CLR_IRQ BIT(10) 772*4882a593Smuzhiyun #define SCDC_UPD_FLAGS_CHG_IRQ BIT(9) 773*4882a593Smuzhiyun #define SCDC_UPD_FLAGS_RD_IRQ BIT(8) 774*4882a593Smuzhiyun #define I2CM_NACK_RCVD_IRQ BIT(2) 775*4882a593Smuzhiyun #define I2CM_READ_REQUEST_IRQ BIT(1) 776*4882a593Smuzhiyun #define I2CM_OP_DONE_IRQ BIT(0) 777*4882a593Smuzhiyun #define MAINUNIT_1_INT_MASK_N 0x3024 778*4882a593Smuzhiyun #define I2CM_NACK_RCVD_MASK_N BIT(2) 779*4882a593Smuzhiyun #define I2CM_READ_REQUEST_MASK_N BIT(1) 780*4882a593Smuzhiyun #define I2CM_OP_DONE_MASK_N BIT(0) 781*4882a593Smuzhiyun #define MAINUNIT_1_INT_CLEAR 0x3028 782*4882a593Smuzhiyun #define I2CM_NACK_RCVD_CLEAR BIT(2) 783*4882a593Smuzhiyun #define I2CM_READ_REQUEST_CLEAR BIT(1) 784*4882a593Smuzhiyun #define I2CM_OP_DONE_CLEAR BIT(0) 785*4882a593Smuzhiyun #define MAINUNIT_1_INT_FORCE 0x302c 786*4882a593Smuzhiyun /* AVPUNIT Interrupt Registers */ 787*4882a593Smuzhiyun #define AVP_INTVEC_INDEX 0x3800 788*4882a593Smuzhiyun #define AVP_0_INT_STATUS 0x3810 789*4882a593Smuzhiyun #define AVP_0_INT_MASK_N 0x3814 790*4882a593Smuzhiyun #define AVP_0_INT_CLEAR 0x3818 791*4882a593Smuzhiyun #define AVP_0_INT_FORCE 0x381c 792*4882a593Smuzhiyun #define AVP_1_INT_STATUS 0x3820 793*4882a593Smuzhiyun #define AVP_1_INT_MASK_N 0x3824 794*4882a593Smuzhiyun #define HDCP14_AUTH_CHG_MASK_N BIT(6) 795*4882a593Smuzhiyun #define AVP_1_INT_CLEAR 0x3828 796*4882a593Smuzhiyun #define AVP_1_INT_FORCE 0x382c 797*4882a593Smuzhiyun #define AVP_2_INT_STATUS 0x3830 798*4882a593Smuzhiyun #define AVP_2_INT_MASK_N 0x3834 799*4882a593Smuzhiyun #define AVP_2_INT_CLEAR 0x3838 800*4882a593Smuzhiyun #define AVP_2_INT_FORCE 0x383c 801*4882a593Smuzhiyun #define AVP_3_INT_STATUS 0x3840 802*4882a593Smuzhiyun #define AVP_3_INT_MASK_N 0x3844 803*4882a593Smuzhiyun #define AVP_3_INT_CLEAR 0x3848 804*4882a593Smuzhiyun #define AVP_3_INT_FORCE 0x384c 805*4882a593Smuzhiyun #define AVP_4_INT_STATUS 0x3850 806*4882a593Smuzhiyun #define AVP_4_INT_MASK_N 0x3854 807*4882a593Smuzhiyun #define AVP_4_INT_CLEAR 0x3858 808*4882a593Smuzhiyun #define AVP_4_INT_FORCE 0x385c 809*4882a593Smuzhiyun #define AVP_5_INT_STATUS 0x3860 810*4882a593Smuzhiyun #define AVP_5_INT_MASK_N 0x3864 811*4882a593Smuzhiyun #define AVP_5_INT_CLEAR 0x3868 812*4882a593Smuzhiyun #define AVP_5_INT_FORCE 0x386c 813*4882a593Smuzhiyun #define AVP_6_INT_STATUS 0x3870 814*4882a593Smuzhiyun #define AVP_6_INT_MASK_N 0x3874 815*4882a593Smuzhiyun #define AVP_6_INT_CLEAR 0x3878 816*4882a593Smuzhiyun #define AVP_6_INT_FORCE 0x387c 817*4882a593Smuzhiyun /* CEC Interrupt Registers */ 818*4882a593Smuzhiyun #define CEC_INT_STATUS 0x4000 819*4882a593Smuzhiyun #define CEC_INT_MASK_N 0x4004 820*4882a593Smuzhiyun #define CEC_INT_CLEAR 0x4008 821*4882a593Smuzhiyun #define CEC_INT_FORCE 0x400c 822*4882a593Smuzhiyun /* eARC RX Interrupt Registers */ 823*4882a593Smuzhiyun #define EARCRX_INTVEC_INDEX 0x4800 824*4882a593Smuzhiyun #define EARCRX_0_INT_STATUS 0x4810 825*4882a593Smuzhiyun #define EARCRX_CMDC_DISCOVERY_TIMEOUT_IRQ BIT(9) 826*4882a593Smuzhiyun #define EARCRX_CMDC_DISCOVERY_DONE_IRQ BIT(8) 827*4882a593Smuzhiyun #define EARCRX_0_INT_MASK_N 0x4814 828*4882a593Smuzhiyun #define EARCRX_0_INT_CLEAR 0x4818 829*4882a593Smuzhiyun #define EARCRX_0_INT_FORCE 0x481c 830*4882a593Smuzhiyun #define EARCRX_1_INT_STATUS 0x4820 831*4882a593Smuzhiyun #define EARCRX_1_INT_MASK_N 0x4824 832*4882a593Smuzhiyun #define EARCRX_1_INT_CLEAR 0x4828 833*4882a593Smuzhiyun #define EARCRX_1_INT_FORCE 0x482c 834*4882a593Smuzhiyun 835*4882a593Smuzhiyun #endif /* __DW_HDMI_QP_H__ */ 836