1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) Rockchip Electronics Co.Ltd 4*4882a593Smuzhiyun * Author: 5*4882a593Smuzhiyun * Algea Cao <algea.cao@rock-chips.com> 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun #ifndef DW_HDMI_QP_CEC_H 8*4882a593Smuzhiyun #define DW_HDMI_QP_CEC_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct dw_hdmi_qp; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct dw_hdmi_qp_cec_ops { 13*4882a593Smuzhiyun void (*enable)(struct dw_hdmi_qp *hdmi); 14*4882a593Smuzhiyun void (*disable)(struct dw_hdmi_qp *hdmi); 15*4882a593Smuzhiyun void (*write)(struct dw_hdmi_qp *hdmi, u32 val, int offset); 16*4882a593Smuzhiyun u32 (*read)(struct dw_hdmi_qp *hdmi, int offset); 17*4882a593Smuzhiyun }; 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun struct dw_hdmi_qp_cec_data { 20*4882a593Smuzhiyun struct dw_hdmi_qp *hdmi; 21*4882a593Smuzhiyun const struct dw_hdmi_qp_cec_ops *ops; 22*4882a593Smuzhiyun int irq; 23*4882a593Smuzhiyun }; 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun #endif 26