1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (c) 2021 Rockchip Electronics Co. Ltd. 4*4882a593Smuzhiyun * Author: Sugar Zhang <sugar.zhang@rock-chips.com> 5*4882a593Smuzhiyun */ 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun #ifndef DW_HDMI_QP_AUDIO_H 8*4882a593Smuzhiyun #define DW_HDMI_QP_AUDIO_H 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct dw_hdmi_qp; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct dw_hdmi_qp_audio_data { 13*4882a593Smuzhiyun phys_addr_t phys; 14*4882a593Smuzhiyun void __iomem *base; 15*4882a593Smuzhiyun int irq; 16*4882a593Smuzhiyun struct dw_hdmi_qp *hdmi; 17*4882a593Smuzhiyun u8 *eld; 18*4882a593Smuzhiyun }; 19*4882a593Smuzhiyun 20*4882a593Smuzhiyun struct dw_hdmi_qp_i2s_audio_data { 21*4882a593Smuzhiyun struct dw_hdmi_qp *hdmi; 22*4882a593Smuzhiyun u8 *eld; 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun void (*write)(struct dw_hdmi_qp *hdmi, u32 val, int offset); 25*4882a593Smuzhiyun u32 (*read)(struct dw_hdmi_qp *hdmi, int offset); 26*4882a593Smuzhiyun void (*mod)(struct dw_hdmi_qp *hdmi, u32 val, u32 mask, u32 reg); 27*4882a593Smuzhiyun }; 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun #endif 30