xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/rk630-tve.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2020 Rockchip Electronics Co. Ltd.
4*4882a593Smuzhiyun  *
5*4882a593Smuzhiyun  * Author: Algea Cao <algea.cao@rock-chips.com>
6*4882a593Smuzhiyun  */
7*4882a593Smuzhiyun 
8*4882a593Smuzhiyun #include <linux/delay.h>
9*4882a593Smuzhiyun #include <linux/i2c.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/mutex.h>
12*4882a593Smuzhiyun #include <linux/mfd/rk630.h>
13*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
14*4882a593Smuzhiyun 
15*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
16*4882a593Smuzhiyun #include <drm/drm_crtc_helper.h>
17*4882a593Smuzhiyun #include <drm/drm_of.h>
18*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #include "../rockchip/rockchip_drm_drv.h"
21*4882a593Smuzhiyun 
22*4882a593Smuzhiyun static const struct drm_display_mode rk630_tve_mode[2] = {
23*4882a593Smuzhiyun 	{ DRM_MODE("720x576i", DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
24*4882a593Smuzhiyun 		   816, 864, 0, 576, 580, 586, 625, 0,
25*4882a593Smuzhiyun 		   DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC |
26*4882a593Smuzhiyun 		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
27*4882a593Smuzhiyun 		   0, },
28*4882a593Smuzhiyun 	{ DRM_MODE("720x480i", DRM_MODE_TYPE_DRIVER, 13500, 720, 753,
29*4882a593Smuzhiyun 		   815, 858, 0, 480, 483, 489, 525, 0,
30*4882a593Smuzhiyun 		   DRM_MODE_FLAG_PHSYNC | DRM_MODE_FLAG_PVSYNC |
31*4882a593Smuzhiyun 		   DRM_MODE_FLAG_INTERLACE | DRM_MODE_FLAG_DBLCLK),
32*4882a593Smuzhiyun 		   0, },
33*4882a593Smuzhiyun };
34*4882a593Smuzhiyun 
35*4882a593Smuzhiyun struct rk630_tve {
36*4882a593Smuzhiyun 	struct device *dev;
37*4882a593Smuzhiyun 	struct drm_connector connector;
38*4882a593Smuzhiyun 	struct drm_bridge bridge;
39*4882a593Smuzhiyun 	struct drm_encoder *encoder;
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun 	struct regmap *grf;
42*4882a593Smuzhiyun 	struct regmap *cru;
43*4882a593Smuzhiyun 	struct regmap *tvemap;
44*4882a593Smuzhiyun 	struct rk630 *parent;
45*4882a593Smuzhiyun 
46*4882a593Smuzhiyun 	int mode;
47*4882a593Smuzhiyun 	int is_4x;
48*4882a593Smuzhiyun 	struct rockchip_drm_sub_dev sub_dev;
49*4882a593Smuzhiyun };
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun enum {
52*4882a593Smuzhiyun 	CVBS_NTSC = 0,
53*4882a593Smuzhiyun 	CVBS_PAL,
54*4882a593Smuzhiyun };
55*4882a593Smuzhiyun 
56*4882a593Smuzhiyun struct env_config {
57*4882a593Smuzhiyun 	u32 offset;
58*4882a593Smuzhiyun 	u32 value;
59*4882a593Smuzhiyun };
60*4882a593Smuzhiyun 
61*4882a593Smuzhiyun static struct env_config ntsc_bt656_config[] = {
62*4882a593Smuzhiyun 	{ BT656_DECODER_CTRL, 0x00000001 },
63*4882a593Smuzhiyun 	{ BT656_DECODER_CROP, 0x00000000 },
64*4882a593Smuzhiyun 	{ BT656_DECODER_SIZE, 0x01e002d0 },
65*4882a593Smuzhiyun 	{ BT656_DECODER_HTOTAL_HS_END, 0x035a003e },
66*4882a593Smuzhiyun 	{ BT656_DECODER_VACT_ST_HACT_ST, 0x00150069 },
67*4882a593Smuzhiyun 	{ BT656_DECODER_VTOTAL_VS_END, 0x020d0003 },
68*4882a593Smuzhiyun 	{ BT656_DECODER_VS_ST_END_F1, 0x01060109 },
69*4882a593Smuzhiyun 	{ BT656_DECODER_DBG_REG, 0x024002d0 },
70*4882a593Smuzhiyun };
71*4882a593Smuzhiyun 
72*4882a593Smuzhiyun static struct env_config ntsc_tve_config[] = {
73*4882a593Smuzhiyun 	{ TVE_MODE_CTRL, 0x000af906 },
74*4882a593Smuzhiyun 	{ TVE_HOR_TIMING1, 0x00c07a81 },
75*4882a593Smuzhiyun 	{ TVE_HOR_TIMING2, 0x169810fc },
76*4882a593Smuzhiyun 	{ TVE_HOR_TIMING3, 0x96b40000 },
77*4882a593Smuzhiyun 	{ TVE_SUB_CAR_FRQ, 0x21f07bd7 },
78*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER1, 0x000a0ffa },
79*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER2, 0x0ff4001a },
80*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER3, 0x00110fd2 },
81*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER4, 0x0fe80051 },
82*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER5, 0x001a0f74 },
83*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER6, 0x0fe600ec },
84*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER7, 0x0ffa0e43 },
85*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER8, 0x08200527 },
86*4882a593Smuzhiyun 	{ TVE_IMAGE_POSITION, 0x001500d6 },
87*4882a593Smuzhiyun 	{ TVE_ROUTING, 0x10088880 },
88*4882a593Smuzhiyun 	{ TVE_SYNC_ADJUST, 0x00000000 },
89*4882a593Smuzhiyun 	{ TVE_STATUS, 0x00000000 },
90*4882a593Smuzhiyun 	{ TVE_CTRL, 0x00000000 },
91*4882a593Smuzhiyun 	{ TVE_INTR_STATUS, 0x00000000 },
92*4882a593Smuzhiyun 	{ TVE_INTR_EN, 0x00000000 },
93*4882a593Smuzhiyun 	{ TVE_INTR_CLR, 0x00000000 },
94*4882a593Smuzhiyun 	{ TVE_COLOR_BUSRT_SAT, 0x0052543c },
95*4882a593Smuzhiyun 	{ TVE_CHROMA_BANDWIDTH, 0x00000002 },
96*4882a593Smuzhiyun 	{ TVE_BRIGHTNESS_CONTRAST, 0x00008300 },
97*4882a593Smuzhiyun 	{ TVE_ID, 0x0a010000 },
98*4882a593Smuzhiyun 	{ TVE_REVISION, 0x00010108 },
99*4882a593Smuzhiyun 	{ TVE_CLAMP, 0x00000000 },
100*4882a593Smuzhiyun };
101*4882a593Smuzhiyun 
102*4882a593Smuzhiyun static struct env_config pal_bt656_config[] = {
103*4882a593Smuzhiyun 	{ BT656_DECODER_CTRL, 0x00000001 },
104*4882a593Smuzhiyun 	{ BT656_DECODER_CROP, 0x00000000 },
105*4882a593Smuzhiyun 	{ BT656_DECODER_SIZE, 0x024002d0 },
106*4882a593Smuzhiyun 	{ BT656_DECODER_HTOTAL_HS_END, 0x0360003f },
107*4882a593Smuzhiyun 	{ BT656_DECODER_VACT_ST_HACT_ST, 0x0016006f },
108*4882a593Smuzhiyun 	{ BT656_DECODER_VTOTAL_VS_END, 0x02710003 },
109*4882a593Smuzhiyun 	{ BT656_DECODER_VS_ST_END_F1, 0x0138013b },
110*4882a593Smuzhiyun 	{ BT656_DECODER_DBG_REG, 0x024002d0 },
111*4882a593Smuzhiyun };
112*4882a593Smuzhiyun 
113*4882a593Smuzhiyun static struct env_config pal_tve_config[] = {
114*4882a593Smuzhiyun 	{ TVE_MODE_CTRL, 0x010ab906 },
115*4882a593Smuzhiyun 	{ TVE_HOR_TIMING1, 0x00c28381 },
116*4882a593Smuzhiyun 	{ TVE_HOR_TIMING2, 0x267d111d },
117*4882a593Smuzhiyun 	{ TVE_HOR_TIMING3, 0x76c00880 },
118*4882a593Smuzhiyun 	{ TVE_SUB_CAR_FRQ, 0x2a098acb },
119*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER1, 0x000a0ffa },
120*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER2, 0x0ff4001a },
121*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER3, 0x00110fd2 },
122*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER4, 0x0fe80051 },
123*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER5, 0x001a0f74 },
124*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER6, 0x0fe600ec },
125*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER7, 0x0ffa0e43 },
126*4882a593Smuzhiyun 	{ TVE_LUMA_FILTER8, 0x08200527 },
127*4882a593Smuzhiyun 	{ TVE_IMAGE_POSITION, 0x001500f6 },
128*4882a593Smuzhiyun 	{ TVE_ROUTING, 0x1000088a },
129*4882a593Smuzhiyun 	{ TVE_SYNC_ADJUST, 0x00000000 },
130*4882a593Smuzhiyun 	{ TVE_STATUS, 0x000000b0 },
131*4882a593Smuzhiyun 	{ TVE_CTRL, 0x00000000 },
132*4882a593Smuzhiyun 	{ TVE_INTR_STATUS, 0x00000000 },
133*4882a593Smuzhiyun 	{ TVE_INTR_EN, 0x00000000 },
134*4882a593Smuzhiyun 	{ TVE_INTR_CLR, 0x00000000 },
135*4882a593Smuzhiyun 	{ TVE_COLOR_BUSRT_SAT, 0x002e553c },
136*4882a593Smuzhiyun 	{ TVE_CHROMA_BANDWIDTH, 0x00000022 },
137*4882a593Smuzhiyun 	{ TVE_BRIGHTNESS_CONTRAST, 0x00008900 },
138*4882a593Smuzhiyun 	{ TVE_ID, 0x0a010000 },
139*4882a593Smuzhiyun 	{ TVE_REVISION, 0x00010108 },
140*4882a593Smuzhiyun 	{ TVE_CLAMP, 0x00000000 },
141*4882a593Smuzhiyun };
142*4882a593Smuzhiyun 
143*4882a593Smuzhiyun static const struct regmap_range rk630_tve_readable_ranges[] = {
144*4882a593Smuzhiyun 	regmap_reg_range(BT656_DECODER_CTRL, BT656_DECODER_DBG_REG),
145*4882a593Smuzhiyun 	regmap_reg_range(TVE_MODE_CTRL, TVE_ROUTING),
146*4882a593Smuzhiyun 	regmap_reg_range(TVE_SYNC_ADJUST, TVE_STATUS),
147*4882a593Smuzhiyun 	regmap_reg_range(TVE_CTRL, TVE_COLOR_BUSRT_SAT),
148*4882a593Smuzhiyun 	regmap_reg_range(TVE_CHROMA_BANDWIDTH, TVE_BRIGHTNESS_CONTRAST),
149*4882a593Smuzhiyun 	regmap_reg_range(TVE_ID, TVE_CLAMP),
150*4882a593Smuzhiyun };
151*4882a593Smuzhiyun 
152*4882a593Smuzhiyun static const struct regmap_access_table rk630_tve_readable_table = {
153*4882a593Smuzhiyun 	.yes_ranges = rk630_tve_readable_ranges,
154*4882a593Smuzhiyun 	.n_yes_ranges = ARRAY_SIZE(rk630_tve_readable_ranges),
155*4882a593Smuzhiyun };
156*4882a593Smuzhiyun 
157*4882a593Smuzhiyun const struct regmap_config rk630_tve_regmap_config = {
158*4882a593Smuzhiyun 	.name = "tve",
159*4882a593Smuzhiyun 	.reg_bits = 32,
160*4882a593Smuzhiyun 	.val_bits = 32,
161*4882a593Smuzhiyun 	.reg_stride = 4,
162*4882a593Smuzhiyun 	.max_register = TVE_MAX_REGISTER,
163*4882a593Smuzhiyun 	.reg_format_endian = REGMAP_ENDIAN_NATIVE,
164*4882a593Smuzhiyun 	.val_format_endian = REGMAP_ENDIAN_NATIVE,
165*4882a593Smuzhiyun 	.rd_table = &rk630_tve_readable_table,
166*4882a593Smuzhiyun };
167*4882a593Smuzhiyun EXPORT_SYMBOL_GPL(rk630_tve_regmap_config);
168*4882a593Smuzhiyun 
bridge_to_tve(struct drm_bridge * bridge)169*4882a593Smuzhiyun static struct rk630_tve *bridge_to_tve(struct drm_bridge *bridge)
170*4882a593Smuzhiyun {
171*4882a593Smuzhiyun 	return container_of(bridge, struct rk630_tve, bridge);
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun 
connector_to_tve(struct drm_connector * connector)174*4882a593Smuzhiyun static struct rk630_tve *connector_to_tve(struct drm_connector *connector)
175*4882a593Smuzhiyun {
176*4882a593Smuzhiyun 	return container_of(connector, struct rk630_tve, connector);
177*4882a593Smuzhiyun }
178*4882a593Smuzhiyun 
rk630_tve_write_block(struct rk630_tve * tve,struct env_config * config,int len)179*4882a593Smuzhiyun static int rk630_tve_write_block(struct rk630_tve *tve,
180*4882a593Smuzhiyun 				 struct env_config *config, int len)
181*4882a593Smuzhiyun {
182*4882a593Smuzhiyun 	int i, ret = 0;
183*4882a593Smuzhiyun 
184*4882a593Smuzhiyun 	for (i = 0; i < len; i++) {
185*4882a593Smuzhiyun 		ret = regmap_write(tve->tvemap, config[i].offset,
186*4882a593Smuzhiyun 				   config[i].value);
187*4882a593Smuzhiyun 		if (ret)
188*4882a593Smuzhiyun 			break;
189*4882a593Smuzhiyun 	}
190*4882a593Smuzhiyun 
191*4882a593Smuzhiyun 	return ret;
192*4882a593Smuzhiyun }
193*4882a593Smuzhiyun 
rk630_tve_cfg_set(struct rk630_tve * tve)194*4882a593Smuzhiyun static int rk630_tve_cfg_set(struct rk630_tve *tve)
195*4882a593Smuzhiyun {
196*4882a593Smuzhiyun 	int ret;
197*4882a593Smuzhiyun 	struct env_config *bt656_cfg, *tve_cfg;
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	switch (tve->mode) {
200*4882a593Smuzhiyun 	case CVBS_PAL:
201*4882a593Smuzhiyun 		dev_dbg(tve->dev, "rk630 PAL\n");
202*4882a593Smuzhiyun 		bt656_cfg = pal_bt656_config;
203*4882a593Smuzhiyun 		tve_cfg = pal_tve_config;
204*4882a593Smuzhiyun 		break;
205*4882a593Smuzhiyun 	case CVBS_NTSC:
206*4882a593Smuzhiyun 		dev_dbg(tve->dev, "rk630 NTSC\n");
207*4882a593Smuzhiyun 		bt656_cfg = ntsc_bt656_config;
208*4882a593Smuzhiyun 		tve_cfg = ntsc_tve_config;
209*4882a593Smuzhiyun 		break;
210*4882a593Smuzhiyun 	default:
211*4882a593Smuzhiyun 		dev_dbg(tve->dev, "mode select err\n");
212*4882a593Smuzhiyun 		return -EINVAL;
213*4882a593Smuzhiyun 	}
214*4882a593Smuzhiyun 
215*4882a593Smuzhiyun 	ret = rk630_tve_write_block(tve, bt656_cfg, 8);
216*4882a593Smuzhiyun 	if (ret) {
217*4882a593Smuzhiyun 		dev_err(tve->dev, "rk630 bt656 write err!\n");
218*4882a593Smuzhiyun 		return ret;
219*4882a593Smuzhiyun 	}
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	if (tve->mode == CVBS_PAL)
222*4882a593Smuzhiyun 		regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON0,
223*4882a593Smuzhiyun 				   SW_TVE_DCLK_POL_MASK |
224*4882a593Smuzhiyun 				   SW_TVE_DCLK_EN_MASK |
225*4882a593Smuzhiyun 				   SW_DCLK_UPSAMPLE_EN_MASK |
226*4882a593Smuzhiyun 				   SW_TVE_MODE_MASK | SW_TVE_EN_MASK,
227*4882a593Smuzhiyun 				   SW_TVE_DCLK_POL(0) | SW_TVE_DCLK_EN(1) |
228*4882a593Smuzhiyun 				   SW_DCLK_UPSAMPLE_EN(tve->is_4x) |
229*4882a593Smuzhiyun 				   SW_TVE_MODE(1) | SW_TVE_EN(1));
230*4882a593Smuzhiyun 	else
231*4882a593Smuzhiyun 		regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON0,
232*4882a593Smuzhiyun 				   SW_TVE_DCLK_POL_MASK |
233*4882a593Smuzhiyun 				   SW_TVE_DCLK_EN_MASK |
234*4882a593Smuzhiyun 				   SW_DCLK_UPSAMPLE_EN_MASK |
235*4882a593Smuzhiyun 				   SW_TVE_MODE_MASK | SW_TVE_EN_MASK,
236*4882a593Smuzhiyun 				   SW_TVE_DCLK_POL(0) | SW_TVE_DCLK_EN(1) |
237*4882a593Smuzhiyun 				   SW_DCLK_UPSAMPLE_EN(tve->is_4x) |
238*4882a593Smuzhiyun 				   SW_TVE_MODE(0) | SW_TVE_EN(1));
239*4882a593Smuzhiyun 
240*4882a593Smuzhiyun 	ret = rk630_tve_write_block(tve, tve_cfg, 27);
241*4882a593Smuzhiyun 	if (ret < 0) {
242*4882a593Smuzhiyun 		dev_err(tve->dev, "rk630 tve write err\n");
243*4882a593Smuzhiyun 		return ret;
244*4882a593Smuzhiyun 	}
245*4882a593Smuzhiyun 
246*4882a593Smuzhiyun 	return ret;
247*4882a593Smuzhiyun }
248*4882a593Smuzhiyun 
rk630_tve_disable(struct rk630_tve * tve)249*4882a593Smuzhiyun static int rk630_tve_disable(struct rk630_tve *tve)
250*4882a593Smuzhiyun {
251*4882a593Smuzhiyun 	regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON3, VDAC_ENDAC0_MASK,
252*4882a593Smuzhiyun 			   VDAC_ENDAC0(0));
253*4882a593Smuzhiyun 
254*4882a593Smuzhiyun 	return 0;
255*4882a593Smuzhiyun }
256*4882a593Smuzhiyun 
rk630_tve_enable(struct rk630_tve * tve)257*4882a593Smuzhiyun static int rk630_tve_enable(struct rk630_tve *tve)
258*4882a593Smuzhiyun {
259*4882a593Smuzhiyun 	int ret, i;
260*4882a593Smuzhiyun 	u32 val = 0;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	dev_dbg(tve->dev, "%s\n", __func__);
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun 	/* config bt656 input gpio*/
265*4882a593Smuzhiyun 	regmap_write(tve->grf, PLUMAGE_GRF_GPIO0A_IOMUX, 0x55555555);
266*4882a593Smuzhiyun 
267*4882a593Smuzhiyun 	regmap_update_bits(tve->grf, PLUMAGE_GRF_GPIO0B_IOMUX, GPIO0B0_SEL_MASK,
268*4882a593Smuzhiyun 			   GPIO0B0_SEL(1));
269*4882a593Smuzhiyun 
270*4882a593Smuzhiyun 	regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON3, VDAC_ENDAC0_MASK,
271*4882a593Smuzhiyun 			   VDAC_ENDAC0(0));
272*4882a593Smuzhiyun 
273*4882a593Smuzhiyun 	ret = rk630_tve_cfg_set(tve);
274*4882a593Smuzhiyun 	if (ret)
275*4882a593Smuzhiyun 		return ret;
276*4882a593Smuzhiyun 
277*4882a593Smuzhiyun 	/*config clk*/
278*4882a593Smuzhiyun 	if (!tve->is_4x) {
279*4882a593Smuzhiyun 		regmap_update_bits(tve->cru, CRU_MODE_CON, CLK_SPLL_MODE_MASK,
280*4882a593Smuzhiyun 				   CLK_SPLL_MODE(2));
281*4882a593Smuzhiyun 	} else {
282*4882a593Smuzhiyun 		regmap_update_bits(tve->cru, CRU_SPLL_CON1, PLLPD0_MASK,
283*4882a593Smuzhiyun 				   PLLPD0(1));
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun 		regmap_update_bits(tve->cru, CRU_MODE_CON, CLK_SPLL_MODE_MASK,
286*4882a593Smuzhiyun 				   CLK_SPLL_MODE(1));
287*4882a593Smuzhiyun 
288*4882a593Smuzhiyun 		regmap_update_bits(tve->cru, CRU_SPLL_CON1, PLLPD0_MASK,
289*4882a593Smuzhiyun 				   PLLPD0(0));
290*4882a593Smuzhiyun 
291*4882a593Smuzhiyun 		for (i = 0; i < 10; i++) {
292*4882a593Smuzhiyun 			usleep_range(1000, 2000);
293*4882a593Smuzhiyun 			regmap_read(tve->cru, CRU_SPLL_CON1, &val);
294*4882a593Smuzhiyun 			if (val & PLL_LOCK) {
295*4882a593Smuzhiyun 				dev_dbg(tve->dev, "rk630 pll locked\n");
296*4882a593Smuzhiyun 				break;
297*4882a593Smuzhiyun 			}
298*4882a593Smuzhiyun 		}
299*4882a593Smuzhiyun 		if (!(val & PLL_LOCK)) {
300*4882a593Smuzhiyun 			dev_err(tve->dev, "rk630 pll unlock\n");
301*4882a593Smuzhiyun 			return -EINVAL;
302*4882a593Smuzhiyun 		}
303*4882a593Smuzhiyun 	}
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun 	/* enable vdac */
306*4882a593Smuzhiyun 	regmap_update_bits(tve->grf, PLUMAGE_GRF_SOC_CON3,
307*4882a593Smuzhiyun 			   VDAC_ENVBG_MASK | VDAC_ENDAC0_MASK,
308*4882a593Smuzhiyun 			   VDAC_ENVBG(1) | VDAC_ENDAC0(1));
309*4882a593Smuzhiyun 
310*4882a593Smuzhiyun 	return 0;
311*4882a593Smuzhiyun }
312*4882a593Smuzhiyun 
313*4882a593Smuzhiyun static enum drm_mode_status
rk630_tve_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)314*4882a593Smuzhiyun rk630_tve_mode_valid(struct drm_connector *connector,
315*4882a593Smuzhiyun 		  struct drm_display_mode *mode)
316*4882a593Smuzhiyun {
317*4882a593Smuzhiyun 	return MODE_OK;
318*4882a593Smuzhiyun }
319*4882a593Smuzhiyun 
320*4882a593Smuzhiyun static int
rk630_tve_get_modes(struct drm_connector * connector)321*4882a593Smuzhiyun rk630_tve_get_modes(struct drm_connector *connector)
322*4882a593Smuzhiyun {
323*4882a593Smuzhiyun 	int count;
324*4882a593Smuzhiyun 	u32 bus_format = MEDIA_BUS_FMT_UYVY8_2X8;
325*4882a593Smuzhiyun 	struct rk630_tve *tve = connector_to_tve(connector);
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun 	for (count = 0; count < ARRAY_SIZE(rk630_tve_mode); count++) {
328*4882a593Smuzhiyun 		struct drm_display_mode *mode_ptr;
329*4882a593Smuzhiyun 
330*4882a593Smuzhiyun 		mode_ptr = drm_mode_duplicate(connector->dev,
331*4882a593Smuzhiyun 					      &rk630_tve_mode[count]);
332*4882a593Smuzhiyun 		if (!mode_ptr) {
333*4882a593Smuzhiyun 			dev_err(tve->dev, "mode duplicate failed\n");
334*4882a593Smuzhiyun 			return -ENOMEM;
335*4882a593Smuzhiyun 		}
336*4882a593Smuzhiyun 
337*4882a593Smuzhiyun 		if (!count)
338*4882a593Smuzhiyun 			mode_ptr->type |= DRM_MODE_TYPE_PREFERRED;
339*4882a593Smuzhiyun 		drm_mode_probed_add(connector, mode_ptr);
340*4882a593Smuzhiyun 	}
341*4882a593Smuzhiyun 	drm_display_info_set_bus_formats(&connector->display_info,
342*4882a593Smuzhiyun 					 &bus_format, 1);
343*4882a593Smuzhiyun 
344*4882a593Smuzhiyun 	return count;
345*4882a593Smuzhiyun }
346*4882a593Smuzhiyun 
347*4882a593Smuzhiyun static enum drm_connector_status
rk630_tve_connector_detect(struct drm_connector * connector,bool force)348*4882a593Smuzhiyun rk630_tve_connector_detect(struct drm_connector *connector,
349*4882a593Smuzhiyun 			bool force)
350*4882a593Smuzhiyun {
351*4882a593Smuzhiyun 	return connector_status_connected;
352*4882a593Smuzhiyun }
353*4882a593Smuzhiyun 
rk630_tve_best_encoder(struct drm_connector * connector)354*4882a593Smuzhiyun static struct drm_encoder *rk630_tve_best_encoder(struct drm_connector *connector)
355*4882a593Smuzhiyun {
356*4882a593Smuzhiyun 	struct rk630_tve *tve = connector_to_tve(connector);
357*4882a593Smuzhiyun 
358*4882a593Smuzhiyun 	return tve->encoder;
359*4882a593Smuzhiyun }
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun static
362*4882a593Smuzhiyun const struct drm_connector_helper_funcs rk630_tve_connector_helper_funcs = {
363*4882a593Smuzhiyun 	.get_modes = rk630_tve_get_modes,
364*4882a593Smuzhiyun 	.mode_valid = rk630_tve_mode_valid,
365*4882a593Smuzhiyun 	.best_encoder = rk630_tve_best_encoder,
366*4882a593Smuzhiyun };
367*4882a593Smuzhiyun 
368*4882a593Smuzhiyun static const struct drm_connector_funcs rk630_tve_connector_funcs = {
369*4882a593Smuzhiyun 	.fill_modes = drm_helper_probe_single_connector_modes,
370*4882a593Smuzhiyun 	.detect = rk630_tve_connector_detect,
371*4882a593Smuzhiyun 	.destroy = drm_connector_cleanup,
372*4882a593Smuzhiyun 	.reset = drm_atomic_helper_connector_reset,
373*4882a593Smuzhiyun 	.atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
374*4882a593Smuzhiyun 	.atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
375*4882a593Smuzhiyun };
376*4882a593Smuzhiyun 
377*4882a593Smuzhiyun static void
rk630_tve_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adjusted_mode)378*4882a593Smuzhiyun rk630_tve_bridge_mode_set(struct drm_bridge *bridge,
379*4882a593Smuzhiyun 			  const struct drm_display_mode *mode,
380*4882a593Smuzhiyun 			  const struct drm_display_mode *adjusted_mode)
381*4882a593Smuzhiyun {
382*4882a593Smuzhiyun 	struct rk630_tve *tve;
383*4882a593Smuzhiyun 
384*4882a593Smuzhiyun 	tve = bridge_to_tve(bridge);
385*4882a593Smuzhiyun 
386*4882a593Smuzhiyun 	if (adjusted_mode->vdisplay == 576)
387*4882a593Smuzhiyun 		tve->mode = CVBS_PAL;
388*4882a593Smuzhiyun 	else
389*4882a593Smuzhiyun 		tve->mode = CVBS_NTSC;
390*4882a593Smuzhiyun }
391*4882a593Smuzhiyun 
rk630_tve_bridge_enable(struct drm_bridge * bridge)392*4882a593Smuzhiyun static void rk630_tve_bridge_enable(struct drm_bridge *bridge)
393*4882a593Smuzhiyun {
394*4882a593Smuzhiyun 	int ret;
395*4882a593Smuzhiyun 	struct rk630_tve *tve = bridge_to_tve(bridge);
396*4882a593Smuzhiyun 
397*4882a593Smuzhiyun 	dev_dbg(tve->dev, "%s\n",  __func__);
398*4882a593Smuzhiyun 	ret = rk630_tve_enable(tve);
399*4882a593Smuzhiyun 	if (ret)
400*4882a593Smuzhiyun 		dev_err(tve->dev, "rk630 enable failed\n");
401*4882a593Smuzhiyun }
402*4882a593Smuzhiyun 
rk630_tve_bridge_disable(struct drm_bridge * bridge)403*4882a593Smuzhiyun static void rk630_tve_bridge_disable(struct drm_bridge *bridge)
404*4882a593Smuzhiyun {
405*4882a593Smuzhiyun 	struct rk630_tve *tve = bridge_to_tve(bridge);
406*4882a593Smuzhiyun 
407*4882a593Smuzhiyun 	dev_dbg(tve->dev, "%s\n",  __func__);
408*4882a593Smuzhiyun 	rk630_tve_disable(tve);
409*4882a593Smuzhiyun }
410*4882a593Smuzhiyun 
rk630_tve_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)411*4882a593Smuzhiyun static int rk630_tve_bridge_attach(struct drm_bridge *bridge,
412*4882a593Smuzhiyun 				   enum drm_bridge_attach_flags flags)
413*4882a593Smuzhiyun {
414*4882a593Smuzhiyun 	struct rk630_tve *tve = bridge_to_tve(bridge);
415*4882a593Smuzhiyun 	int ret;
416*4882a593Smuzhiyun 
417*4882a593Smuzhiyun 	if (!bridge->encoder) {
418*4882a593Smuzhiyun 		dev_err(tve->dev, "Parent encoder object not found\n");
419*4882a593Smuzhiyun 		return -ENODEV;
420*4882a593Smuzhiyun 	}
421*4882a593Smuzhiyun 
422*4882a593Smuzhiyun 	tve->encoder = bridge->encoder;
423*4882a593Smuzhiyun 	ret = drm_connector_init(bridge->dev, &tve->connector,
424*4882a593Smuzhiyun 				 &rk630_tve_connector_funcs,
425*4882a593Smuzhiyun 				 DRM_MODE_CONNECTOR_TV);
426*4882a593Smuzhiyun 	if (ret) {
427*4882a593Smuzhiyun 		dev_err(tve->dev, "Failed to initialize connector\n");
428*4882a593Smuzhiyun 		return ret;
429*4882a593Smuzhiyun 	}
430*4882a593Smuzhiyun 
431*4882a593Smuzhiyun 	drm_connector_helper_add(&tve->connector,
432*4882a593Smuzhiyun 				 &rk630_tve_connector_helper_funcs);
433*4882a593Smuzhiyun 	ret = drm_connector_attach_encoder(&tve->connector,
434*4882a593Smuzhiyun 					   bridge->encoder);
435*4882a593Smuzhiyun 
436*4882a593Smuzhiyun 	if (ret)
437*4882a593Smuzhiyun 		dev_err(tve->dev, "rk630 attach failed ret:%d", ret);
438*4882a593Smuzhiyun 	tve->sub_dev.connector = &tve->connector;
439*4882a593Smuzhiyun 	tve->sub_dev.of_node = tve->dev->of_node;
440*4882a593Smuzhiyun 	rockchip_drm_register_sub_dev(&tve->sub_dev);
441*4882a593Smuzhiyun 	tve->connector.interlace_allowed = 1;
442*4882a593Smuzhiyun 
443*4882a593Smuzhiyun 	return ret;
444*4882a593Smuzhiyun }
445*4882a593Smuzhiyun 
rk1000_bridge_detach(struct drm_bridge * bridge)446*4882a593Smuzhiyun static void rk1000_bridge_detach(struct drm_bridge *bridge)
447*4882a593Smuzhiyun {
448*4882a593Smuzhiyun 	struct rk630_tve *tve = bridge_to_tve(bridge);
449*4882a593Smuzhiyun 
450*4882a593Smuzhiyun 	rockchip_drm_unregister_sub_dev(&tve->sub_dev);
451*4882a593Smuzhiyun }
452*4882a593Smuzhiyun 
453*4882a593Smuzhiyun static struct drm_bridge_funcs rk630_tve_bridge_funcs = {
454*4882a593Smuzhiyun 	.enable = rk630_tve_bridge_enable,
455*4882a593Smuzhiyun 	.disable = rk630_tve_bridge_disable,
456*4882a593Smuzhiyun 	.mode_set = rk630_tve_bridge_mode_set,
457*4882a593Smuzhiyun 	.attach = rk630_tve_bridge_attach,
458*4882a593Smuzhiyun 	.detach = rk1000_bridge_detach,
459*4882a593Smuzhiyun };
460*4882a593Smuzhiyun 
rk630_tve_probe(struct platform_device * pdev)461*4882a593Smuzhiyun static int rk630_tve_probe(struct platform_device *pdev)
462*4882a593Smuzhiyun {
463*4882a593Smuzhiyun 	struct rk630 *rk630 = dev_get_drvdata(pdev->dev.parent);
464*4882a593Smuzhiyun 	struct rk630_tve *tve;
465*4882a593Smuzhiyun 	struct device *dev = &pdev->dev;
466*4882a593Smuzhiyun 
467*4882a593Smuzhiyun 	if (!of_device_is_available(dev->of_node))
468*4882a593Smuzhiyun 		return -ENODEV;
469*4882a593Smuzhiyun 
470*4882a593Smuzhiyun 	tve = devm_kzalloc(dev, sizeof(*tve), GFP_KERNEL);
471*4882a593Smuzhiyun 	if (!tve)
472*4882a593Smuzhiyun 		return -ENOMEM;
473*4882a593Smuzhiyun 
474*4882a593Smuzhiyun 	tve->dev = dev;
475*4882a593Smuzhiyun 	tve->parent = rk630;
476*4882a593Smuzhiyun 	platform_set_drvdata(pdev, tve);
477*4882a593Smuzhiyun 
478*4882a593Smuzhiyun 	tve->grf = rk630->grf;
479*4882a593Smuzhiyun 	tve->cru = rk630->cru;
480*4882a593Smuzhiyun 	tve->tvemap = rk630->tve;
481*4882a593Smuzhiyun 	if (!tve->grf | !tve->cru | !tve->tvemap)
482*4882a593Smuzhiyun 		return -ENODEV;
483*4882a593Smuzhiyun 
484*4882a593Smuzhiyun 	tve->mode = CVBS_PAL;
485*4882a593Smuzhiyun 
486*4882a593Smuzhiyun 	tve->bridge.funcs = &rk630_tve_bridge_funcs;
487*4882a593Smuzhiyun 	tve->bridge.of_node = tve->dev->of_node;
488*4882a593Smuzhiyun 
489*4882a593Smuzhiyun 	drm_bridge_add(&tve->bridge);
490*4882a593Smuzhiyun 
491*4882a593Smuzhiyun 	dev_dbg(tve->dev, "rk630 probe tve ok\n");
492*4882a593Smuzhiyun 
493*4882a593Smuzhiyun 	return 0;
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun 
rk630_tve_remove(struct platform_device * pdev)496*4882a593Smuzhiyun static int rk630_tve_remove(struct platform_device *pdev)
497*4882a593Smuzhiyun {
498*4882a593Smuzhiyun 	struct rk630_tve *tve = platform_get_drvdata(pdev);
499*4882a593Smuzhiyun 
500*4882a593Smuzhiyun 	drm_bridge_remove(&tve->bridge);
501*4882a593Smuzhiyun 
502*4882a593Smuzhiyun 	return 0;
503*4882a593Smuzhiyun }
504*4882a593Smuzhiyun 
505*4882a593Smuzhiyun static const struct of_device_id rk630_tve_dt_ids[] = {
506*4882a593Smuzhiyun 	{ .compatible = "rockchip,rk630-tve" },
507*4882a593Smuzhiyun 	{ }
508*4882a593Smuzhiyun };
509*4882a593Smuzhiyun 
510*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, rk630_tve_dt_ids);
511*4882a593Smuzhiyun 
512*4882a593Smuzhiyun static struct platform_driver rk630_tve_driver = {
513*4882a593Smuzhiyun 	.driver = {
514*4882a593Smuzhiyun 		.name = "rk630-tve",
515*4882a593Smuzhiyun 		.of_match_table = of_match_ptr(rk630_tve_dt_ids),
516*4882a593Smuzhiyun 	},
517*4882a593Smuzhiyun 	.probe = rk630_tve_probe,
518*4882a593Smuzhiyun 	.remove = rk630_tve_remove,
519*4882a593Smuzhiyun };
520*4882a593Smuzhiyun module_platform_driver(rk630_tve_driver);
521*4882a593Smuzhiyun 
522*4882a593Smuzhiyun MODULE_AUTHOR("Algea Cao <Algea.cao@rock-chips.com>");
523*4882a593Smuzhiyun MODULE_DESCRIPTION("ROCKCHIP rk630 TVE Driver");
524*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
525