xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/bridge/parade-ps8640.c (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun  * Copyright (c) 2016 MediaTek Inc.
4*4882a593Smuzhiyun  */
5*4882a593Smuzhiyun 
6*4882a593Smuzhiyun #include <linux/delay.h>
7*4882a593Smuzhiyun #include <linux/err.h>
8*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
9*4882a593Smuzhiyun #include <linux/i2c.h>
10*4882a593Smuzhiyun #include <linux/module.h>
11*4882a593Smuzhiyun #include <linux/of_graph.h>
12*4882a593Smuzhiyun #include <linux/regulator/consumer.h>
13*4882a593Smuzhiyun 
14*4882a593Smuzhiyun #include <drm/drm_bridge.h>
15*4882a593Smuzhiyun #include <drm/drm_mipi_dsi.h>
16*4882a593Smuzhiyun #include <drm/drm_of.h>
17*4882a593Smuzhiyun #include <drm/drm_panel.h>
18*4882a593Smuzhiyun #include <drm/drm_print.h>
19*4882a593Smuzhiyun 
20*4882a593Smuzhiyun #define PAGE2_GPIO_H		0xa7
21*4882a593Smuzhiyun #define PS_GPIO9		BIT(1)
22*4882a593Smuzhiyun #define PAGE2_I2C_BYPASS	0xea
23*4882a593Smuzhiyun #define I2C_BYPASS_EN		0xd0
24*4882a593Smuzhiyun #define PAGE2_MCS_EN		0xf3
25*4882a593Smuzhiyun #define MCS_EN			BIT(0)
26*4882a593Smuzhiyun #define PAGE3_SET_ADD		0xfe
27*4882a593Smuzhiyun #define VDO_CTL_ADD		0x13
28*4882a593Smuzhiyun #define VDO_DIS			0x18
29*4882a593Smuzhiyun #define VDO_EN			0x1c
30*4882a593Smuzhiyun #define DP_NUM_LANES		4
31*4882a593Smuzhiyun 
32*4882a593Smuzhiyun /*
33*4882a593Smuzhiyun  * PS8640 uses multiple addresses:
34*4882a593Smuzhiyun  * page[0]: for DP control
35*4882a593Smuzhiyun  * page[1]: for VIDEO Bridge
36*4882a593Smuzhiyun  * page[2]: for control top
37*4882a593Smuzhiyun  * page[3]: for DSI Link Control1
38*4882a593Smuzhiyun  * page[4]: for MIPI Phy
39*4882a593Smuzhiyun  * page[5]: for VPLL
40*4882a593Smuzhiyun  * page[6]: for DSI Link Control2
41*4882a593Smuzhiyun  * page[7]: for SPI ROM mapping
42*4882a593Smuzhiyun  */
43*4882a593Smuzhiyun enum page_addr_offset {
44*4882a593Smuzhiyun 	PAGE0_DP_CNTL = 0,
45*4882a593Smuzhiyun 	PAGE1_VDO_BDG,
46*4882a593Smuzhiyun 	PAGE2_TOP_CNTL,
47*4882a593Smuzhiyun 	PAGE3_DSI_CNTL1,
48*4882a593Smuzhiyun 	PAGE4_MIPI_PHY,
49*4882a593Smuzhiyun 	PAGE5_VPLL,
50*4882a593Smuzhiyun 	PAGE6_DSI_CNTL2,
51*4882a593Smuzhiyun 	PAGE7_SPI_CNTL,
52*4882a593Smuzhiyun 	MAX_DEVS
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun 
55*4882a593Smuzhiyun enum ps8640_vdo_control {
56*4882a593Smuzhiyun 	DISABLE = VDO_DIS,
57*4882a593Smuzhiyun 	ENABLE = VDO_EN,
58*4882a593Smuzhiyun };
59*4882a593Smuzhiyun 
60*4882a593Smuzhiyun struct ps8640 {
61*4882a593Smuzhiyun 	struct drm_bridge bridge;
62*4882a593Smuzhiyun 	struct drm_bridge *panel_bridge;
63*4882a593Smuzhiyun 	struct mipi_dsi_device *dsi;
64*4882a593Smuzhiyun 	struct i2c_client *page[MAX_DEVS];
65*4882a593Smuzhiyun 	struct regulator_bulk_data supplies[2];
66*4882a593Smuzhiyun 	struct gpio_desc *gpio_reset;
67*4882a593Smuzhiyun 	struct gpio_desc *gpio_powerdown;
68*4882a593Smuzhiyun 	bool powered;
69*4882a593Smuzhiyun };
70*4882a593Smuzhiyun 
bridge_to_ps8640(struct drm_bridge * e)71*4882a593Smuzhiyun static inline struct ps8640 *bridge_to_ps8640(struct drm_bridge *e)
72*4882a593Smuzhiyun {
73*4882a593Smuzhiyun 	return container_of(e, struct ps8640, bridge);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun 
ps8640_bridge_vdo_control(struct ps8640 * ps_bridge,const enum ps8640_vdo_control ctrl)76*4882a593Smuzhiyun static int ps8640_bridge_vdo_control(struct ps8640 *ps_bridge,
77*4882a593Smuzhiyun 				     const enum ps8640_vdo_control ctrl)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun 	struct i2c_client *client = ps_bridge->page[PAGE3_DSI_CNTL1];
80*4882a593Smuzhiyun 	u8 vdo_ctrl_buf[] = { VDO_CTL_ADD, ctrl };
81*4882a593Smuzhiyun 	int ret;
82*4882a593Smuzhiyun 
83*4882a593Smuzhiyun 	ret = i2c_smbus_write_i2c_block_data(client, PAGE3_SET_ADD,
84*4882a593Smuzhiyun 					     sizeof(vdo_ctrl_buf),
85*4882a593Smuzhiyun 					     vdo_ctrl_buf);
86*4882a593Smuzhiyun 	if (ret < 0) {
87*4882a593Smuzhiyun 		DRM_ERROR("failed to %sable VDO: %d\n",
88*4882a593Smuzhiyun 			  ctrl == ENABLE ? "en" : "dis", ret);
89*4882a593Smuzhiyun 		return ret;
90*4882a593Smuzhiyun 	}
91*4882a593Smuzhiyun 
92*4882a593Smuzhiyun 	return 0;
93*4882a593Smuzhiyun }
94*4882a593Smuzhiyun 
ps8640_bridge_poweron(struct ps8640 * ps_bridge)95*4882a593Smuzhiyun static void ps8640_bridge_poweron(struct ps8640 *ps_bridge)
96*4882a593Smuzhiyun {
97*4882a593Smuzhiyun 	struct i2c_client *client = ps_bridge->page[PAGE2_TOP_CNTL];
98*4882a593Smuzhiyun 	unsigned long timeout;
99*4882a593Smuzhiyun 	int ret, status;
100*4882a593Smuzhiyun 
101*4882a593Smuzhiyun 	if (ps_bridge->powered)
102*4882a593Smuzhiyun 		return;
103*4882a593Smuzhiyun 
104*4882a593Smuzhiyun 	ret = regulator_bulk_enable(ARRAY_SIZE(ps_bridge->supplies),
105*4882a593Smuzhiyun 				    ps_bridge->supplies);
106*4882a593Smuzhiyun 	if (ret < 0) {
107*4882a593Smuzhiyun 		DRM_ERROR("cannot enable regulators %d\n", ret);
108*4882a593Smuzhiyun 		return;
109*4882a593Smuzhiyun 	}
110*4882a593Smuzhiyun 
111*4882a593Smuzhiyun 	gpiod_set_value(ps_bridge->gpio_powerdown, 0);
112*4882a593Smuzhiyun 	gpiod_set_value(ps_bridge->gpio_reset, 1);
113*4882a593Smuzhiyun 	usleep_range(2000, 2500);
114*4882a593Smuzhiyun 	gpiod_set_value(ps_bridge->gpio_reset, 0);
115*4882a593Smuzhiyun 
116*4882a593Smuzhiyun 	/*
117*4882a593Smuzhiyun 	 * Wait for the ps8640 embedded MCU to be ready
118*4882a593Smuzhiyun 	 * First wait 200ms and then check the MCU ready flag every 20ms
119*4882a593Smuzhiyun 	 */
120*4882a593Smuzhiyun 	msleep(200);
121*4882a593Smuzhiyun 
122*4882a593Smuzhiyun 	timeout = jiffies + msecs_to_jiffies(200) + 1;
123*4882a593Smuzhiyun 
124*4882a593Smuzhiyun 	while (time_is_after_jiffies(timeout)) {
125*4882a593Smuzhiyun 		status = i2c_smbus_read_byte_data(client, PAGE2_GPIO_H);
126*4882a593Smuzhiyun 		if (status < 0) {
127*4882a593Smuzhiyun 			DRM_ERROR("failed read PAGE2_GPIO_H: %d\n", status);
128*4882a593Smuzhiyun 			goto err_regulators_disable;
129*4882a593Smuzhiyun 		}
130*4882a593Smuzhiyun 		if ((status & PS_GPIO9) == PS_GPIO9)
131*4882a593Smuzhiyun 			break;
132*4882a593Smuzhiyun 
133*4882a593Smuzhiyun 		msleep(20);
134*4882a593Smuzhiyun 	}
135*4882a593Smuzhiyun 
136*4882a593Smuzhiyun 	msleep(50);
137*4882a593Smuzhiyun 
138*4882a593Smuzhiyun 	/*
139*4882a593Smuzhiyun 	 * The Manufacturer Command Set (MCS) is a device dependent interface
140*4882a593Smuzhiyun 	 * intended for factory programming of the display module default
141*4882a593Smuzhiyun 	 * parameters. Once the display module is configured, the MCS shall be
142*4882a593Smuzhiyun 	 * disabled by the manufacturer. Once disabled, all MCS commands are
143*4882a593Smuzhiyun 	 * ignored by the display interface.
144*4882a593Smuzhiyun 	 */
145*4882a593Smuzhiyun 	status = i2c_smbus_read_byte_data(client, PAGE2_MCS_EN);
146*4882a593Smuzhiyun 	if (status < 0) {
147*4882a593Smuzhiyun 		DRM_ERROR("failed read PAGE2_MCS_EN: %d\n", status);
148*4882a593Smuzhiyun 		goto err_regulators_disable;
149*4882a593Smuzhiyun 	}
150*4882a593Smuzhiyun 
151*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(client, PAGE2_MCS_EN,
152*4882a593Smuzhiyun 					status & ~MCS_EN);
153*4882a593Smuzhiyun 	if (ret < 0) {
154*4882a593Smuzhiyun 		DRM_ERROR("failed write PAGE2_MCS_EN: %d\n", ret);
155*4882a593Smuzhiyun 		goto err_regulators_disable;
156*4882a593Smuzhiyun 	}
157*4882a593Smuzhiyun 
158*4882a593Smuzhiyun 	/* Switch access edp panel's edid through i2c */
159*4882a593Smuzhiyun 	ret = i2c_smbus_write_byte_data(client, PAGE2_I2C_BYPASS,
160*4882a593Smuzhiyun 					I2C_BYPASS_EN);
161*4882a593Smuzhiyun 	if (ret < 0) {
162*4882a593Smuzhiyun 		DRM_ERROR("failed write PAGE2_I2C_BYPASS: %d\n", ret);
163*4882a593Smuzhiyun 		goto err_regulators_disable;
164*4882a593Smuzhiyun 	}
165*4882a593Smuzhiyun 
166*4882a593Smuzhiyun 	ps_bridge->powered = true;
167*4882a593Smuzhiyun 
168*4882a593Smuzhiyun 	return;
169*4882a593Smuzhiyun 
170*4882a593Smuzhiyun err_regulators_disable:
171*4882a593Smuzhiyun 	regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
172*4882a593Smuzhiyun 			       ps_bridge->supplies);
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun 
ps8640_bridge_poweroff(struct ps8640 * ps_bridge)175*4882a593Smuzhiyun static void ps8640_bridge_poweroff(struct ps8640 *ps_bridge)
176*4882a593Smuzhiyun {
177*4882a593Smuzhiyun 	int ret;
178*4882a593Smuzhiyun 
179*4882a593Smuzhiyun 	if (!ps_bridge->powered)
180*4882a593Smuzhiyun 		return;
181*4882a593Smuzhiyun 
182*4882a593Smuzhiyun 	gpiod_set_value(ps_bridge->gpio_reset, 1);
183*4882a593Smuzhiyun 	gpiod_set_value(ps_bridge->gpio_powerdown, 1);
184*4882a593Smuzhiyun 	ret = regulator_bulk_disable(ARRAY_SIZE(ps_bridge->supplies),
185*4882a593Smuzhiyun 				     ps_bridge->supplies);
186*4882a593Smuzhiyun 	if (ret < 0)
187*4882a593Smuzhiyun 		DRM_ERROR("cannot disable regulators %d\n", ret);
188*4882a593Smuzhiyun 
189*4882a593Smuzhiyun 	ps_bridge->powered = false;
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun 
ps8640_pre_enable(struct drm_bridge * bridge)192*4882a593Smuzhiyun static void ps8640_pre_enable(struct drm_bridge *bridge)
193*4882a593Smuzhiyun {
194*4882a593Smuzhiyun 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
195*4882a593Smuzhiyun 	int ret;
196*4882a593Smuzhiyun 
197*4882a593Smuzhiyun 	ps8640_bridge_poweron(ps_bridge);
198*4882a593Smuzhiyun 
199*4882a593Smuzhiyun 	ret = ps8640_bridge_vdo_control(ps_bridge, ENABLE);
200*4882a593Smuzhiyun 	if (ret < 0)
201*4882a593Smuzhiyun 		ps8640_bridge_poweroff(ps_bridge);
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun 
ps8640_post_disable(struct drm_bridge * bridge)204*4882a593Smuzhiyun static void ps8640_post_disable(struct drm_bridge *bridge)
205*4882a593Smuzhiyun {
206*4882a593Smuzhiyun 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	ps8640_bridge_vdo_control(ps_bridge, DISABLE);
209*4882a593Smuzhiyun 	ps8640_bridge_poweroff(ps_bridge);
210*4882a593Smuzhiyun }
211*4882a593Smuzhiyun 
ps8640_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)212*4882a593Smuzhiyun static int ps8640_bridge_attach(struct drm_bridge *bridge,
213*4882a593Smuzhiyun 				enum drm_bridge_attach_flags flags)
214*4882a593Smuzhiyun {
215*4882a593Smuzhiyun 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
216*4882a593Smuzhiyun 	struct device *dev = &ps_bridge->page[0]->dev;
217*4882a593Smuzhiyun 	struct device_node *in_ep, *dsi_node;
218*4882a593Smuzhiyun 	struct mipi_dsi_device *dsi;
219*4882a593Smuzhiyun 	struct mipi_dsi_host *host;
220*4882a593Smuzhiyun 	int ret;
221*4882a593Smuzhiyun 	const struct mipi_dsi_device_info info = { .type = "ps8640",
222*4882a593Smuzhiyun 						   .channel = 0,
223*4882a593Smuzhiyun 						   .node = NULL,
224*4882a593Smuzhiyun 						 };
225*4882a593Smuzhiyun 
226*4882a593Smuzhiyun 	if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR))
227*4882a593Smuzhiyun 		return -EINVAL;
228*4882a593Smuzhiyun 
229*4882a593Smuzhiyun 	/* port@0 is ps8640 dsi input port */
230*4882a593Smuzhiyun 	in_ep = of_graph_get_endpoint_by_regs(dev->of_node, 0, -1);
231*4882a593Smuzhiyun 	if (!in_ep)
232*4882a593Smuzhiyun 		return -ENODEV;
233*4882a593Smuzhiyun 
234*4882a593Smuzhiyun 	dsi_node = of_graph_get_remote_port_parent(in_ep);
235*4882a593Smuzhiyun 	of_node_put(in_ep);
236*4882a593Smuzhiyun 	if (!dsi_node)
237*4882a593Smuzhiyun 		return -ENODEV;
238*4882a593Smuzhiyun 
239*4882a593Smuzhiyun 	host = of_find_mipi_dsi_host_by_node(dsi_node);
240*4882a593Smuzhiyun 	of_node_put(dsi_node);
241*4882a593Smuzhiyun 	if (!host)
242*4882a593Smuzhiyun 		return -ENODEV;
243*4882a593Smuzhiyun 
244*4882a593Smuzhiyun 	dsi = mipi_dsi_device_register_full(host, &info);
245*4882a593Smuzhiyun 	if (IS_ERR(dsi)) {
246*4882a593Smuzhiyun 		dev_err(dev, "failed to create dsi device\n");
247*4882a593Smuzhiyun 		ret = PTR_ERR(dsi);
248*4882a593Smuzhiyun 		return ret;
249*4882a593Smuzhiyun 	}
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun 	ps_bridge->dsi = dsi;
252*4882a593Smuzhiyun 
253*4882a593Smuzhiyun 	dsi->host = host;
254*4882a593Smuzhiyun 	dsi->mode_flags = MIPI_DSI_MODE_VIDEO |
255*4882a593Smuzhiyun 			  MIPI_DSI_MODE_VIDEO_SYNC_PULSE;
256*4882a593Smuzhiyun 	dsi->format = MIPI_DSI_FMT_RGB888;
257*4882a593Smuzhiyun 	dsi->lanes = DP_NUM_LANES;
258*4882a593Smuzhiyun 	ret = mipi_dsi_attach(dsi);
259*4882a593Smuzhiyun 	if (ret)
260*4882a593Smuzhiyun 		goto err_dsi_attach;
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun 	/* Attach the panel-bridge to the dsi bridge */
263*4882a593Smuzhiyun 	return drm_bridge_attach(bridge->encoder, ps_bridge->panel_bridge,
264*4882a593Smuzhiyun 				 &ps_bridge->bridge, flags);
265*4882a593Smuzhiyun 
266*4882a593Smuzhiyun err_dsi_attach:
267*4882a593Smuzhiyun 	mipi_dsi_device_unregister(dsi);
268*4882a593Smuzhiyun 	return ret;
269*4882a593Smuzhiyun }
270*4882a593Smuzhiyun 
ps8640_bridge_get_edid(struct drm_bridge * bridge,struct drm_connector * connector)271*4882a593Smuzhiyun static struct edid *ps8640_bridge_get_edid(struct drm_bridge *bridge,
272*4882a593Smuzhiyun 					   struct drm_connector *connector)
273*4882a593Smuzhiyun {
274*4882a593Smuzhiyun 	struct ps8640 *ps_bridge = bridge_to_ps8640(bridge);
275*4882a593Smuzhiyun 	bool poweroff = !ps_bridge->powered;
276*4882a593Smuzhiyun 	struct edid *edid;
277*4882a593Smuzhiyun 
278*4882a593Smuzhiyun 	/*
279*4882a593Smuzhiyun 	 * When we end calling get_edid() triggered by an ioctl, i.e
280*4882a593Smuzhiyun 	 *
281*4882a593Smuzhiyun 	 *   drm_mode_getconnector (ioctl)
282*4882a593Smuzhiyun 	 *     -> drm_helper_probe_single_connector_modes
283*4882a593Smuzhiyun 	 *        -> drm_bridge_connector_get_modes
284*4882a593Smuzhiyun 	 *           -> ps8640_bridge_get_edid
285*4882a593Smuzhiyun 	 *
286*4882a593Smuzhiyun 	 * We need to make sure that what we need is enabled before reading
287*4882a593Smuzhiyun 	 * EDID, for this chip, we need to do a full poweron, otherwise it will
288*4882a593Smuzhiyun 	 * fail.
289*4882a593Smuzhiyun 	 */
290*4882a593Smuzhiyun 	drm_bridge_chain_pre_enable(bridge);
291*4882a593Smuzhiyun 
292*4882a593Smuzhiyun 	edid = drm_get_edid(connector,
293*4882a593Smuzhiyun 			    ps_bridge->page[PAGE0_DP_CNTL]->adapter);
294*4882a593Smuzhiyun 
295*4882a593Smuzhiyun 	/*
296*4882a593Smuzhiyun 	 * If we call the get_edid() function without having enabled the chip
297*4882a593Smuzhiyun 	 * before, return the chip to its original power state.
298*4882a593Smuzhiyun 	 */
299*4882a593Smuzhiyun 	if (poweroff)
300*4882a593Smuzhiyun 		drm_bridge_chain_post_disable(bridge);
301*4882a593Smuzhiyun 
302*4882a593Smuzhiyun 	return edid;
303*4882a593Smuzhiyun }
304*4882a593Smuzhiyun 
305*4882a593Smuzhiyun static const struct drm_bridge_funcs ps8640_bridge_funcs = {
306*4882a593Smuzhiyun 	.attach = ps8640_bridge_attach,
307*4882a593Smuzhiyun 	.get_edid = ps8640_bridge_get_edid,
308*4882a593Smuzhiyun 	.post_disable = ps8640_post_disable,
309*4882a593Smuzhiyun 	.pre_enable = ps8640_pre_enable,
310*4882a593Smuzhiyun };
311*4882a593Smuzhiyun 
ps8640_probe(struct i2c_client * client)312*4882a593Smuzhiyun static int ps8640_probe(struct i2c_client *client)
313*4882a593Smuzhiyun {
314*4882a593Smuzhiyun 	struct device *dev = &client->dev;
315*4882a593Smuzhiyun 	struct device_node *np = dev->of_node;
316*4882a593Smuzhiyun 	struct ps8640 *ps_bridge;
317*4882a593Smuzhiyun 	struct drm_panel *panel;
318*4882a593Smuzhiyun 	int ret;
319*4882a593Smuzhiyun 	u32 i;
320*4882a593Smuzhiyun 
321*4882a593Smuzhiyun 	ps_bridge = devm_kzalloc(dev, sizeof(*ps_bridge), GFP_KERNEL);
322*4882a593Smuzhiyun 	if (!ps_bridge)
323*4882a593Smuzhiyun 		return -ENOMEM;
324*4882a593Smuzhiyun 
325*4882a593Smuzhiyun 	/* port@1 is ps8640 output port */
326*4882a593Smuzhiyun 	ret = drm_of_find_panel_or_bridge(np, 1, 0, &panel, NULL);
327*4882a593Smuzhiyun 	if (ret < 0)
328*4882a593Smuzhiyun 		return ret;
329*4882a593Smuzhiyun 	if (!panel)
330*4882a593Smuzhiyun 		return -ENODEV;
331*4882a593Smuzhiyun 
332*4882a593Smuzhiyun 	ps_bridge->panel_bridge = devm_drm_panel_bridge_add(dev, panel);
333*4882a593Smuzhiyun 	if (IS_ERR(ps_bridge->panel_bridge))
334*4882a593Smuzhiyun 		return PTR_ERR(ps_bridge->panel_bridge);
335*4882a593Smuzhiyun 
336*4882a593Smuzhiyun 	ps_bridge->supplies[0].supply = "vdd12";
337*4882a593Smuzhiyun 	ps_bridge->supplies[1].supply = "vdd33";
338*4882a593Smuzhiyun 	ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(ps_bridge->supplies),
339*4882a593Smuzhiyun 				      ps_bridge->supplies);
340*4882a593Smuzhiyun 	if (ret)
341*4882a593Smuzhiyun 		return ret;
342*4882a593Smuzhiyun 
343*4882a593Smuzhiyun 	ps_bridge->gpio_powerdown = devm_gpiod_get(&client->dev, "powerdown",
344*4882a593Smuzhiyun 						   GPIOD_OUT_HIGH);
345*4882a593Smuzhiyun 	if (IS_ERR(ps_bridge->gpio_powerdown))
346*4882a593Smuzhiyun 		return PTR_ERR(ps_bridge->gpio_powerdown);
347*4882a593Smuzhiyun 
348*4882a593Smuzhiyun 	/*
349*4882a593Smuzhiyun 	 * Assert the reset to avoid the bridge being initialized prematurely
350*4882a593Smuzhiyun 	 */
351*4882a593Smuzhiyun 	ps_bridge->gpio_reset = devm_gpiod_get(&client->dev, "reset",
352*4882a593Smuzhiyun 					       GPIOD_OUT_HIGH);
353*4882a593Smuzhiyun 	if (IS_ERR(ps_bridge->gpio_reset))
354*4882a593Smuzhiyun 		return PTR_ERR(ps_bridge->gpio_reset);
355*4882a593Smuzhiyun 
356*4882a593Smuzhiyun 	ps_bridge->bridge.funcs = &ps8640_bridge_funcs;
357*4882a593Smuzhiyun 	ps_bridge->bridge.of_node = dev->of_node;
358*4882a593Smuzhiyun 	ps_bridge->bridge.ops = DRM_BRIDGE_OP_EDID;
359*4882a593Smuzhiyun 	ps_bridge->bridge.type = DRM_MODE_CONNECTOR_eDP;
360*4882a593Smuzhiyun 
361*4882a593Smuzhiyun 	ps_bridge->page[PAGE0_DP_CNTL] = client;
362*4882a593Smuzhiyun 
363*4882a593Smuzhiyun 	for (i = 1; i < ARRAY_SIZE(ps_bridge->page); i++) {
364*4882a593Smuzhiyun 		ps_bridge->page[i] = devm_i2c_new_dummy_device(&client->dev,
365*4882a593Smuzhiyun 							     client->adapter,
366*4882a593Smuzhiyun 							     client->addr + i);
367*4882a593Smuzhiyun 		if (IS_ERR(ps_bridge->page[i])) {
368*4882a593Smuzhiyun 			dev_err(dev, "failed i2c dummy device, address %02x\n",
369*4882a593Smuzhiyun 				client->addr + i);
370*4882a593Smuzhiyun 			return PTR_ERR(ps_bridge->page[i]);
371*4882a593Smuzhiyun 		}
372*4882a593Smuzhiyun 	}
373*4882a593Smuzhiyun 
374*4882a593Smuzhiyun 	i2c_set_clientdata(client, ps_bridge);
375*4882a593Smuzhiyun 
376*4882a593Smuzhiyun 	drm_bridge_add(&ps_bridge->bridge);
377*4882a593Smuzhiyun 
378*4882a593Smuzhiyun 	return 0;
379*4882a593Smuzhiyun }
380*4882a593Smuzhiyun 
ps8640_remove(struct i2c_client * client)381*4882a593Smuzhiyun static int ps8640_remove(struct i2c_client *client)
382*4882a593Smuzhiyun {
383*4882a593Smuzhiyun 	struct ps8640 *ps_bridge = i2c_get_clientdata(client);
384*4882a593Smuzhiyun 
385*4882a593Smuzhiyun 	drm_bridge_remove(&ps_bridge->bridge);
386*4882a593Smuzhiyun 
387*4882a593Smuzhiyun 	return 0;
388*4882a593Smuzhiyun }
389*4882a593Smuzhiyun 
390*4882a593Smuzhiyun static const struct of_device_id ps8640_match[] = {
391*4882a593Smuzhiyun 	{ .compatible = "parade,ps8640" },
392*4882a593Smuzhiyun 	{ }
393*4882a593Smuzhiyun };
394*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, ps8640_match);
395*4882a593Smuzhiyun 
396*4882a593Smuzhiyun static struct i2c_driver ps8640_driver = {
397*4882a593Smuzhiyun 	.probe_new = ps8640_probe,
398*4882a593Smuzhiyun 	.remove = ps8640_remove,
399*4882a593Smuzhiyun 	.driver = {
400*4882a593Smuzhiyun 		.name = "ps8640",
401*4882a593Smuzhiyun 		.of_match_table = ps8640_match,
402*4882a593Smuzhiyun 	},
403*4882a593Smuzhiyun };
404*4882a593Smuzhiyun module_i2c_driver(ps8640_driver);
405*4882a593Smuzhiyun 
406*4882a593Smuzhiyun MODULE_AUTHOR("Jitao Shi <jitao.shi@mediatek.com>");
407*4882a593Smuzhiyun MODULE_AUTHOR("CK Hu <ck.hu@mediatek.com>");
408*4882a593Smuzhiyun MODULE_AUTHOR("Enric Balletbo i Serra <enric.balletbo@collabora.com>");
409*4882a593Smuzhiyun MODULE_DESCRIPTION("PARADE ps8640 DSI-eDP converter driver");
410*4882a593Smuzhiyun MODULE_LICENSE("GPL v2");
411