1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright(c) 2016, Analogix Semiconductor. All rights reserved. 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef _ANALOGIX_I2C_TXCOMMON_H_ 6*4882a593Smuzhiyun #define _ANALOGIX_I2C_TXCOMMON_H_ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun /***************************************************************/ 9*4882a593Smuzhiyun /* Register definitions for TX_P2 */ 10*4882a593Smuzhiyun /***************************************************************/ 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun /* 13*4882a593Smuzhiyun * Core Register Definitions 14*4882a593Smuzhiyun */ 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun /* Device ID Low Byte Register */ 17*4882a593Smuzhiyun #define SP_DEVICE_IDL_REG 0x02 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun /* Device ID High Byte Register */ 20*4882a593Smuzhiyun #define SP_DEVICE_IDH_REG 0x03 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun /* Device version register */ 23*4882a593Smuzhiyun #define SP_DEVICE_VERSION_REG 0x04 24*4882a593Smuzhiyun 25*4882a593Smuzhiyun /* Power Down Control Register */ 26*4882a593Smuzhiyun #define SP_POWERDOWN_CTRL_REG 0x05 27*4882a593Smuzhiyun #define SP_REGISTER_PD BIT(7) 28*4882a593Smuzhiyun #define SP_HDCP_PD BIT(5) 29*4882a593Smuzhiyun #define SP_AUDIO_PD BIT(4) 30*4882a593Smuzhiyun #define SP_VIDEO_PD BIT(3) 31*4882a593Smuzhiyun #define SP_LINK_PD BIT(2) 32*4882a593Smuzhiyun #define SP_TOTAL_PD BIT(1) 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Reset Control Register 1 */ 35*4882a593Smuzhiyun #define SP_RESET_CTRL1_REG 0x06 36*4882a593Smuzhiyun #define SP_MISC_RST BIT(7) 37*4882a593Smuzhiyun #define SP_VIDCAP_RST BIT(6) 38*4882a593Smuzhiyun #define SP_VIDFIF_RST BIT(5) 39*4882a593Smuzhiyun #define SP_AUDFIF_RST BIT(4) 40*4882a593Smuzhiyun #define SP_AUDCAP_RST BIT(3) 41*4882a593Smuzhiyun #define SP_HDCP_RST BIT(2) 42*4882a593Smuzhiyun #define SP_SW_RST BIT(1) 43*4882a593Smuzhiyun #define SP_HW_RST BIT(0) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun /* Reset Control Register 2 */ 46*4882a593Smuzhiyun #define SP_RESET_CTRL2_REG 0x07 47*4882a593Smuzhiyun #define SP_AUX_RST BIT(2) 48*4882a593Smuzhiyun #define SP_SERDES_FIFO_RST BIT(1) 49*4882a593Smuzhiyun #define SP_I2C_REG_RST BIT(0) 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun /* Video Control Register 1 */ 52*4882a593Smuzhiyun #define SP_VID_CTRL1_REG 0x08 53*4882a593Smuzhiyun #define SP_VIDEO_EN BIT(7) 54*4882a593Smuzhiyun #define SP_VIDEO_MUTE BIT(2) 55*4882a593Smuzhiyun #define SP_DE_GEN BIT(1) 56*4882a593Smuzhiyun #define SP_DEMUX BIT(0) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* Video Control Register 2 */ 59*4882a593Smuzhiyun #define SP_VID_CTRL2_REG 0x09 60*4882a593Smuzhiyun #define SP_IN_COLOR_F_MASK 0x03 61*4882a593Smuzhiyun #define SP_IN_YC_BIT_SEL BIT(2) 62*4882a593Smuzhiyun #define SP_IN_BPC_MASK 0x70 63*4882a593Smuzhiyun #define SP_IN_BPC_SHIFT 4 64*4882a593Smuzhiyun # define SP_IN_BPC_12BIT 0x03 65*4882a593Smuzhiyun # define SP_IN_BPC_10BIT 0x02 66*4882a593Smuzhiyun # define SP_IN_BPC_8BIT 0x01 67*4882a593Smuzhiyun # define SP_IN_BPC_6BIT 0x00 68*4882a593Smuzhiyun #define SP_IN_D_RANGE BIT(7) 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* Video Control Register 3 */ 71*4882a593Smuzhiyun #define SP_VID_CTRL3_REG 0x0a 72*4882a593Smuzhiyun #define SP_HPD_OUT BIT(6) 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun /* Video Control Register 5 */ 75*4882a593Smuzhiyun #define SP_VID_CTRL5_REG 0x0c 76*4882a593Smuzhiyun #define SP_CSC_STD_SEL BIT(7) 77*4882a593Smuzhiyun #define SP_XVYCC_RNG_LMT BIT(6) 78*4882a593Smuzhiyun #define SP_RANGE_Y2R BIT(5) 79*4882a593Smuzhiyun #define SP_CSPACE_Y2R BIT(4) 80*4882a593Smuzhiyun #define SP_RGB_RNG_LMT BIT(3) 81*4882a593Smuzhiyun #define SP_Y_RNG_LMT BIT(2) 82*4882a593Smuzhiyun #define SP_RANGE_R2Y BIT(1) 83*4882a593Smuzhiyun #define SP_CSPACE_R2Y BIT(0) 84*4882a593Smuzhiyun 85*4882a593Smuzhiyun /* Video Control Register 6 */ 86*4882a593Smuzhiyun #define SP_VID_CTRL6_REG 0x0d 87*4882a593Smuzhiyun #define SP_TEST_PATTERN_EN BIT(7) 88*4882a593Smuzhiyun #define SP_VIDEO_PROCESS_EN BIT(6) 89*4882a593Smuzhiyun #define SP_VID_US_MODE BIT(3) 90*4882a593Smuzhiyun #define SP_VID_DS_MODE BIT(2) 91*4882a593Smuzhiyun #define SP_UP_SAMPLE BIT(1) 92*4882a593Smuzhiyun #define SP_DOWN_SAMPLE BIT(0) 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun /* Video Control Register 8 */ 95*4882a593Smuzhiyun #define SP_VID_CTRL8_REG 0x0f 96*4882a593Smuzhiyun #define SP_VID_VRES_TH BIT(0) 97*4882a593Smuzhiyun 98*4882a593Smuzhiyun /* Total Line Status Low Byte Register */ 99*4882a593Smuzhiyun #define SP_TOTAL_LINE_STAL_REG 0x24 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun /* Total Line Status High Byte Register */ 102*4882a593Smuzhiyun #define SP_TOTAL_LINE_STAH_REG 0x25 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Active Line Status Low Byte Register */ 105*4882a593Smuzhiyun #define SP_ACT_LINE_STAL_REG 0x26 106*4882a593Smuzhiyun 107*4882a593Smuzhiyun /* Active Line Status High Byte Register */ 108*4882a593Smuzhiyun #define SP_ACT_LINE_STAH_REG 0x27 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun /* Vertical Front Porch Status Register */ 111*4882a593Smuzhiyun #define SP_V_F_PORCH_STA_REG 0x28 112*4882a593Smuzhiyun 113*4882a593Smuzhiyun /* Vertical SYNC Width Status Register */ 114*4882a593Smuzhiyun #define SP_V_SYNC_STA_REG 0x29 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun /* Vertical Back Porch Status Register */ 117*4882a593Smuzhiyun #define SP_V_B_PORCH_STA_REG 0x2a 118*4882a593Smuzhiyun 119*4882a593Smuzhiyun /* Total Pixel Status Low Byte Register */ 120*4882a593Smuzhiyun #define SP_TOTAL_PIXEL_STAL_REG 0x2b 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun /* Total Pixel Status High Byte Register */ 123*4882a593Smuzhiyun #define SP_TOTAL_PIXEL_STAH_REG 0x2c 124*4882a593Smuzhiyun 125*4882a593Smuzhiyun /* Active Pixel Status Low Byte Register */ 126*4882a593Smuzhiyun #define SP_ACT_PIXEL_STAL_REG 0x2d 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun /* Active Pixel Status High Byte Register */ 129*4882a593Smuzhiyun #define SP_ACT_PIXEL_STAH_REG 0x2e 130*4882a593Smuzhiyun 131*4882a593Smuzhiyun /* Horizontal Front Porch Status Low Byte Register */ 132*4882a593Smuzhiyun #define SP_H_F_PORCH_STAL_REG 0x2f 133*4882a593Smuzhiyun 134*4882a593Smuzhiyun /* Horizontal Front Porch Statys High Byte Register */ 135*4882a593Smuzhiyun #define SP_H_F_PORCH_STAH_REG 0x30 136*4882a593Smuzhiyun 137*4882a593Smuzhiyun /* Horizontal SYNC Width Status Low Byte Register */ 138*4882a593Smuzhiyun #define SP_H_SYNC_STAL_REG 0x31 139*4882a593Smuzhiyun 140*4882a593Smuzhiyun /* Horizontal SYNC Width Status High Byte Register */ 141*4882a593Smuzhiyun #define SP_H_SYNC_STAH_REG 0x32 142*4882a593Smuzhiyun 143*4882a593Smuzhiyun /* Horizontal Back Porch Status Low Byte Register */ 144*4882a593Smuzhiyun #define SP_H_B_PORCH_STAL_REG 0x33 145*4882a593Smuzhiyun 146*4882a593Smuzhiyun /* Horizontal Back Porch Status High Byte Register */ 147*4882a593Smuzhiyun #define SP_H_B_PORCH_STAH_REG 0x34 148*4882a593Smuzhiyun 149*4882a593Smuzhiyun /* InfoFrame AVI Packet DB1 Register */ 150*4882a593Smuzhiyun #define SP_INFOFRAME_AVI_DB1_REG 0x70 151*4882a593Smuzhiyun 152*4882a593Smuzhiyun /* Bit Control Specific Register */ 153*4882a593Smuzhiyun #define SP_BIT_CTRL_SPECIFIC_REG 0x80 154*4882a593Smuzhiyun #define SP_BIT_CTRL_SELECT_SHIFT 1 155*4882a593Smuzhiyun #define SP_ENABLE_BIT_CTRL BIT(0) 156*4882a593Smuzhiyun 157*4882a593Smuzhiyun /* InfoFrame Audio Packet DB1 Register */ 158*4882a593Smuzhiyun #define SP_INFOFRAME_AUD_DB1_REG 0x83 159*4882a593Smuzhiyun 160*4882a593Smuzhiyun /* InfoFrame MPEG Packet DB1 Register */ 161*4882a593Smuzhiyun #define SP_INFOFRAME_MPEG_DB1_REG 0xb0 162*4882a593Smuzhiyun 163*4882a593Smuzhiyun /* Audio Channel Status Registers */ 164*4882a593Smuzhiyun #define SP_AUD_CH_STATUS_BASE 0xd0 165*4882a593Smuzhiyun 166*4882a593Smuzhiyun /* Audio Channel Num Register 5 */ 167*4882a593Smuzhiyun #define SP_I2S_CHANNEL_NUM_MASK 0xe0 168*4882a593Smuzhiyun # define SP_I2S_CH_NUM_1 (0x00 << 5) 169*4882a593Smuzhiyun # define SP_I2S_CH_NUM_2 (0x01 << 5) 170*4882a593Smuzhiyun # define SP_I2S_CH_NUM_3 (0x02 << 5) 171*4882a593Smuzhiyun # define SP_I2S_CH_NUM_4 (0x03 << 5) 172*4882a593Smuzhiyun # define SP_I2S_CH_NUM_5 (0x04 << 5) 173*4882a593Smuzhiyun # define SP_I2S_CH_NUM_6 (0x05 << 5) 174*4882a593Smuzhiyun # define SP_I2S_CH_NUM_7 (0x06 << 5) 175*4882a593Smuzhiyun # define SP_I2S_CH_NUM_8 (0x07 << 5) 176*4882a593Smuzhiyun #define SP_EXT_VUCP BIT(2) 177*4882a593Smuzhiyun #define SP_VBIT BIT(1) 178*4882a593Smuzhiyun #define SP_AUDIO_LAYOUT BIT(0) 179*4882a593Smuzhiyun 180*4882a593Smuzhiyun /* Analog Debug Register 1 */ 181*4882a593Smuzhiyun #define SP_ANALOG_DEBUG1_REG 0xdc 182*4882a593Smuzhiyun 183*4882a593Smuzhiyun /* Analog Debug Register 2 */ 184*4882a593Smuzhiyun #define SP_ANALOG_DEBUG2_REG 0xdd 185*4882a593Smuzhiyun #define SP_FORCE_SW_OFF_BYPASS 0x20 186*4882a593Smuzhiyun #define SP_XTAL_FRQ 0x1c 187*4882a593Smuzhiyun # define SP_XTAL_FRQ_19M2 (0x00 << 2) 188*4882a593Smuzhiyun # define SP_XTAL_FRQ_24M (0x01 << 2) 189*4882a593Smuzhiyun # define SP_XTAL_FRQ_25M (0x02 << 2) 190*4882a593Smuzhiyun # define SP_XTAL_FRQ_26M (0x03 << 2) 191*4882a593Smuzhiyun # define SP_XTAL_FRQ_27M (0x04 << 2) 192*4882a593Smuzhiyun # define SP_XTAL_FRQ_38M4 (0x05 << 2) 193*4882a593Smuzhiyun # define SP_XTAL_FRQ_52M (0x06 << 2) 194*4882a593Smuzhiyun #define SP_POWERON_TIME_1P5MS 0x03 195*4882a593Smuzhiyun 196*4882a593Smuzhiyun /* Analog Control 0 Register */ 197*4882a593Smuzhiyun #define SP_ANALOG_CTRL0_REG 0xe1 198*4882a593Smuzhiyun 199*4882a593Smuzhiyun /* Common Interrupt Status Register 1 */ 200*4882a593Smuzhiyun #define SP_COMMON_INT_STATUS_BASE (0xf1 - 1) 201*4882a593Smuzhiyun #define SP_PLL_LOCK_CHG 0x40 202*4882a593Smuzhiyun 203*4882a593Smuzhiyun /* Common Interrupt Status Register 2 */ 204*4882a593Smuzhiyun #define SP_COMMON_INT_STATUS2 0xf2 205*4882a593Smuzhiyun #define SP_HDCP_AUTH_CHG BIT(1) 206*4882a593Smuzhiyun #define SP_HDCP_AUTH_DONE BIT(0) 207*4882a593Smuzhiyun 208*4882a593Smuzhiyun #define SP_HDCP_LINK_CHECK_FAIL BIT(0) 209*4882a593Smuzhiyun 210*4882a593Smuzhiyun /* Common Interrupt Status Register 4 */ 211*4882a593Smuzhiyun #define SP_COMMON_INT_STATUS4_REG 0xf4 212*4882a593Smuzhiyun #define SP_HPD_IRQ BIT(6) 213*4882a593Smuzhiyun #define SP_HPD_ESYNC_ERR BIT(4) 214*4882a593Smuzhiyun #define SP_HPD_CHG BIT(2) 215*4882a593Smuzhiyun #define SP_HPD_LOST BIT(1) 216*4882a593Smuzhiyun #define SP_HPD_PLUG BIT(0) 217*4882a593Smuzhiyun 218*4882a593Smuzhiyun /* DP Interrupt Status Register */ 219*4882a593Smuzhiyun #define SP_DP_INT_STATUS1_REG 0xf7 220*4882a593Smuzhiyun #define SP_TRAINING_FINISH BIT(5) 221*4882a593Smuzhiyun #define SP_POLLING_ERR BIT(4) 222*4882a593Smuzhiyun 223*4882a593Smuzhiyun /* Common Interrupt Mask Register */ 224*4882a593Smuzhiyun #define SP_COMMON_INT_MASK_BASE (0xf8 - 1) 225*4882a593Smuzhiyun 226*4882a593Smuzhiyun #define SP_COMMON_INT_MASK4_REG 0xfb 227*4882a593Smuzhiyun 228*4882a593Smuzhiyun /* DP Interrupts Mask Register */ 229*4882a593Smuzhiyun #define SP_DP_INT_MASK1_REG 0xfe 230*4882a593Smuzhiyun 231*4882a593Smuzhiyun /* Interrupt Control Register */ 232*4882a593Smuzhiyun #define SP_INT_CTRL_REG 0xff 233*4882a593Smuzhiyun 234*4882a593Smuzhiyun #endif /* _ANALOGIX_I2C_TXCOMMON_H_ */ 235