1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0-only
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * Analog Devices ADV7511 HDMI transmitter driver
4*4882a593Smuzhiyun *
5*4882a593Smuzhiyun * Copyright 2012 Analog Devices Inc.
6*4882a593Smuzhiyun */
7*4882a593Smuzhiyun
8*4882a593Smuzhiyun #include <linux/clk.h>
9*4882a593Smuzhiyun #include <linux/device.h>
10*4882a593Smuzhiyun #include <linux/gpio/consumer.h>
11*4882a593Smuzhiyun #include <linux/module.h>
12*4882a593Smuzhiyun #include <linux/of_device.h>
13*4882a593Smuzhiyun #include <linux/slab.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <media/cec.h>
16*4882a593Smuzhiyun
17*4882a593Smuzhiyun #include <drm/drm_atomic.h>
18*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
19*4882a593Smuzhiyun #include <drm/drm_edid.h>
20*4882a593Smuzhiyun #include <drm/drm_print.h>
21*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
22*4882a593Smuzhiyun
23*4882a593Smuzhiyun #include "adv7511.h"
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun /* ADI recommended values for proper operation. */
26*4882a593Smuzhiyun static const struct reg_sequence adv7511_fixed_registers[] = {
27*4882a593Smuzhiyun { 0x98, 0x03 },
28*4882a593Smuzhiyun { 0x9a, 0xe0 },
29*4882a593Smuzhiyun { 0x9c, 0x30 },
30*4882a593Smuzhiyun { 0x9d, 0x61 },
31*4882a593Smuzhiyun { 0xa2, 0xa4 },
32*4882a593Smuzhiyun { 0xa3, 0xa4 },
33*4882a593Smuzhiyun { 0xe0, 0xd0 },
34*4882a593Smuzhiyun { 0xf9, 0x00 },
35*4882a593Smuzhiyun { 0x55, 0x02 },
36*4882a593Smuzhiyun };
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
39*4882a593Smuzhiyun * Register access
40*4882a593Smuzhiyun */
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static const uint8_t adv7511_register_defaults[] = {
43*4882a593Smuzhiyun 0x12, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 00 */
44*4882a593Smuzhiyun 0x00, 0x00, 0x01, 0x0e, 0xbc, 0x18, 0x01, 0x13,
45*4882a593Smuzhiyun 0x25, 0x37, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 10 */
46*4882a593Smuzhiyun 0x46, 0x62, 0x04, 0xa8, 0x00, 0x00, 0x1c, 0x84,
47*4882a593Smuzhiyun 0x1c, 0xbf, 0x04, 0xa8, 0x1e, 0x70, 0x02, 0x1e, /* 20 */
48*4882a593Smuzhiyun 0x00, 0x00, 0x04, 0xa8, 0x08, 0x12, 0x1b, 0xac,
49*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 30 */
50*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x80, 0x00, 0x00, 0x00, 0xb0,
51*4882a593Smuzhiyun 0x00, 0x50, 0x90, 0x7e, 0x79, 0x70, 0x00, 0x00, /* 40 */
52*4882a593Smuzhiyun 0x00, 0xa8, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00,
53*4882a593Smuzhiyun 0x00, 0x00, 0x02, 0x0d, 0x00, 0x00, 0x00, 0x00, /* 50 */
54*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
55*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 60 */
56*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
57*4882a593Smuzhiyun 0x01, 0x0a, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 70 */
58*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
59*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* 80 */
60*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
61*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0xc0, 0x00, 0x00, 0x00, /* 90 */
62*4882a593Smuzhiyun 0x0b, 0x02, 0x00, 0x18, 0x5a, 0x60, 0x00, 0x00,
63*4882a593Smuzhiyun 0x00, 0x00, 0x80, 0x80, 0x08, 0x04, 0x00, 0x00, /* a0 */
64*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x40, 0x00, 0x00, 0x40, 0x14,
65*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* b0 */
66*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
67*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, /* c0 */
68*4882a593Smuzhiyun 0x00, 0x03, 0x00, 0x00, 0x02, 0x00, 0x01, 0x04,
69*4882a593Smuzhiyun 0x30, 0xff, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, /* d0 */
70*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x10, 0x01,
71*4882a593Smuzhiyun 0x80, 0x75, 0x00, 0x00, 0x60, 0x00, 0x00, 0x00, /* e0 */
72*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
73*4882a593Smuzhiyun 0x00, 0x00, 0x00, 0x00, 0x00, 0x75, 0x11, 0x00, /* f0 */
74*4882a593Smuzhiyun 0x00, 0x7c, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
75*4882a593Smuzhiyun };
76*4882a593Smuzhiyun
adv7511_register_volatile(struct device * dev,unsigned int reg)77*4882a593Smuzhiyun static bool adv7511_register_volatile(struct device *dev, unsigned int reg)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun switch (reg) {
80*4882a593Smuzhiyun case ADV7511_REG_CHIP_REVISION:
81*4882a593Smuzhiyun case ADV7511_REG_SPDIF_FREQ:
82*4882a593Smuzhiyun case ADV7511_REG_CTS_AUTOMATIC1:
83*4882a593Smuzhiyun case ADV7511_REG_CTS_AUTOMATIC2:
84*4882a593Smuzhiyun case ADV7511_REG_VIC_DETECTED:
85*4882a593Smuzhiyun case ADV7511_REG_VIC_SEND:
86*4882a593Smuzhiyun case ADV7511_REG_AUX_VIC_DETECTED:
87*4882a593Smuzhiyun case ADV7511_REG_STATUS:
88*4882a593Smuzhiyun case ADV7511_REG_GC(1):
89*4882a593Smuzhiyun case ADV7511_REG_INT(0):
90*4882a593Smuzhiyun case ADV7511_REG_INT(1):
91*4882a593Smuzhiyun case ADV7511_REG_PLL_STATUS:
92*4882a593Smuzhiyun case ADV7511_REG_AN(0):
93*4882a593Smuzhiyun case ADV7511_REG_AN(1):
94*4882a593Smuzhiyun case ADV7511_REG_AN(2):
95*4882a593Smuzhiyun case ADV7511_REG_AN(3):
96*4882a593Smuzhiyun case ADV7511_REG_AN(4):
97*4882a593Smuzhiyun case ADV7511_REG_AN(5):
98*4882a593Smuzhiyun case ADV7511_REG_AN(6):
99*4882a593Smuzhiyun case ADV7511_REG_AN(7):
100*4882a593Smuzhiyun case ADV7511_REG_HDCP_STATUS:
101*4882a593Smuzhiyun case ADV7511_REG_BCAPS:
102*4882a593Smuzhiyun case ADV7511_REG_BKSV(0):
103*4882a593Smuzhiyun case ADV7511_REG_BKSV(1):
104*4882a593Smuzhiyun case ADV7511_REG_BKSV(2):
105*4882a593Smuzhiyun case ADV7511_REG_BKSV(3):
106*4882a593Smuzhiyun case ADV7511_REG_BKSV(4):
107*4882a593Smuzhiyun case ADV7511_REG_DDC_STATUS:
108*4882a593Smuzhiyun case ADV7511_REG_EDID_READ_CTRL:
109*4882a593Smuzhiyun case ADV7511_REG_BSTATUS(0):
110*4882a593Smuzhiyun case ADV7511_REG_BSTATUS(1):
111*4882a593Smuzhiyun case ADV7511_REG_CHIP_ID_HIGH:
112*4882a593Smuzhiyun case ADV7511_REG_CHIP_ID_LOW:
113*4882a593Smuzhiyun return true;
114*4882a593Smuzhiyun }
115*4882a593Smuzhiyun
116*4882a593Smuzhiyun return false;
117*4882a593Smuzhiyun }
118*4882a593Smuzhiyun
119*4882a593Smuzhiyun static const struct regmap_config adv7511_regmap_config = {
120*4882a593Smuzhiyun .reg_bits = 8,
121*4882a593Smuzhiyun .val_bits = 8,
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun .max_register = 0xff,
124*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
125*4882a593Smuzhiyun .reg_defaults_raw = adv7511_register_defaults,
126*4882a593Smuzhiyun .num_reg_defaults_raw = ARRAY_SIZE(adv7511_register_defaults),
127*4882a593Smuzhiyun
128*4882a593Smuzhiyun .volatile_reg = adv7511_register_volatile,
129*4882a593Smuzhiyun };
130*4882a593Smuzhiyun
131*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
132*4882a593Smuzhiyun * Hardware configuration
133*4882a593Smuzhiyun */
134*4882a593Smuzhiyun
adv7511_set_colormap(struct adv7511 * adv7511,bool enable,const uint16_t * coeff,unsigned int scaling_factor)135*4882a593Smuzhiyun static void adv7511_set_colormap(struct adv7511 *adv7511, bool enable,
136*4882a593Smuzhiyun const uint16_t *coeff,
137*4882a593Smuzhiyun unsigned int scaling_factor)
138*4882a593Smuzhiyun {
139*4882a593Smuzhiyun unsigned int i;
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(1),
142*4882a593Smuzhiyun ADV7511_CSC_UPDATE_MODE, ADV7511_CSC_UPDATE_MODE);
143*4882a593Smuzhiyun
144*4882a593Smuzhiyun if (enable) {
145*4882a593Smuzhiyun for (i = 0; i < 12; ++i) {
146*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap,
147*4882a593Smuzhiyun ADV7511_REG_CSC_UPPER(i),
148*4882a593Smuzhiyun 0x1f, coeff[i] >> 8);
149*4882a593Smuzhiyun regmap_write(adv7511->regmap,
150*4882a593Smuzhiyun ADV7511_REG_CSC_LOWER(i),
151*4882a593Smuzhiyun coeff[i] & 0xff);
152*4882a593Smuzhiyun }
153*4882a593Smuzhiyun }
154*4882a593Smuzhiyun
155*4882a593Smuzhiyun if (enable)
156*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(0),
157*4882a593Smuzhiyun 0xe0, 0x80 | (scaling_factor << 5));
158*4882a593Smuzhiyun else
159*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(0),
160*4882a593Smuzhiyun 0x80, 0x00);
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_CSC_UPPER(1),
163*4882a593Smuzhiyun ADV7511_CSC_UPDATE_MODE, 0);
164*4882a593Smuzhiyun }
165*4882a593Smuzhiyun
adv7511_packet_enable(struct adv7511 * adv7511,unsigned int packet)166*4882a593Smuzhiyun static int adv7511_packet_enable(struct adv7511 *adv7511, unsigned int packet)
167*4882a593Smuzhiyun {
168*4882a593Smuzhiyun if (packet & 0xff)
169*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_PACKET_ENABLE0,
170*4882a593Smuzhiyun packet, 0xff);
171*4882a593Smuzhiyun
172*4882a593Smuzhiyun if (packet & 0xff00) {
173*4882a593Smuzhiyun packet >>= 8;
174*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_PACKET_ENABLE1,
175*4882a593Smuzhiyun packet, 0xff);
176*4882a593Smuzhiyun }
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun return 0;
179*4882a593Smuzhiyun }
180*4882a593Smuzhiyun
adv7511_packet_disable(struct adv7511 * adv7511,unsigned int packet)181*4882a593Smuzhiyun static int adv7511_packet_disable(struct adv7511 *adv7511, unsigned int packet)
182*4882a593Smuzhiyun {
183*4882a593Smuzhiyun if (packet & 0xff)
184*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_PACKET_ENABLE0,
185*4882a593Smuzhiyun packet, 0x00);
186*4882a593Smuzhiyun
187*4882a593Smuzhiyun if (packet & 0xff00) {
188*4882a593Smuzhiyun packet >>= 8;
189*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_PACKET_ENABLE1,
190*4882a593Smuzhiyun packet, 0x00);
191*4882a593Smuzhiyun }
192*4882a593Smuzhiyun
193*4882a593Smuzhiyun return 0;
194*4882a593Smuzhiyun }
195*4882a593Smuzhiyun
196*4882a593Smuzhiyun /* Coefficients for adv7511 color space conversion */
197*4882a593Smuzhiyun static const uint16_t adv7511_csc_ycbcr_to_rgb[] = {
198*4882a593Smuzhiyun 0x0734, 0x04ad, 0x0000, 0x1c1b,
199*4882a593Smuzhiyun 0x1ddc, 0x04ad, 0x1f24, 0x0135,
200*4882a593Smuzhiyun 0x0000, 0x04ad, 0x087c, 0x1b77,
201*4882a593Smuzhiyun };
202*4882a593Smuzhiyun
adv7511_set_config_csc(struct adv7511 * adv7511,struct drm_connector * connector,bool rgb,bool hdmi_mode)203*4882a593Smuzhiyun static void adv7511_set_config_csc(struct adv7511 *adv7511,
204*4882a593Smuzhiyun struct drm_connector *connector,
205*4882a593Smuzhiyun bool rgb, bool hdmi_mode)
206*4882a593Smuzhiyun {
207*4882a593Smuzhiyun struct adv7511_video_config config;
208*4882a593Smuzhiyun bool output_format_422, output_format_ycbcr;
209*4882a593Smuzhiyun unsigned int mode;
210*4882a593Smuzhiyun uint8_t infoframe[17];
211*4882a593Smuzhiyun
212*4882a593Smuzhiyun config.hdmi_mode = hdmi_mode;
213*4882a593Smuzhiyun
214*4882a593Smuzhiyun hdmi_avi_infoframe_init(&config.avi_infoframe);
215*4882a593Smuzhiyun
216*4882a593Smuzhiyun config.avi_infoframe.scan_mode = HDMI_SCAN_MODE_UNDERSCAN;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun if (rgb) {
219*4882a593Smuzhiyun config.csc_enable = false;
220*4882a593Smuzhiyun config.avi_infoframe.colorspace = HDMI_COLORSPACE_RGB;
221*4882a593Smuzhiyun } else {
222*4882a593Smuzhiyun config.csc_scaling_factor = ADV7511_CSC_SCALING_4;
223*4882a593Smuzhiyun config.csc_coefficents = adv7511_csc_ycbcr_to_rgb;
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun if ((connector->display_info.color_formats &
226*4882a593Smuzhiyun DRM_COLOR_FORMAT_YCRCB422) &&
227*4882a593Smuzhiyun config.hdmi_mode) {
228*4882a593Smuzhiyun config.csc_enable = false;
229*4882a593Smuzhiyun config.avi_infoframe.colorspace =
230*4882a593Smuzhiyun HDMI_COLORSPACE_YUV422;
231*4882a593Smuzhiyun } else {
232*4882a593Smuzhiyun config.csc_enable = true;
233*4882a593Smuzhiyun config.avi_infoframe.colorspace = HDMI_COLORSPACE_RGB;
234*4882a593Smuzhiyun }
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
237*4882a593Smuzhiyun if (config.hdmi_mode) {
238*4882a593Smuzhiyun mode = ADV7511_HDMI_CFG_MODE_HDMI;
239*4882a593Smuzhiyun
240*4882a593Smuzhiyun switch (config.avi_infoframe.colorspace) {
241*4882a593Smuzhiyun case HDMI_COLORSPACE_YUV444:
242*4882a593Smuzhiyun output_format_422 = false;
243*4882a593Smuzhiyun output_format_ycbcr = true;
244*4882a593Smuzhiyun break;
245*4882a593Smuzhiyun case HDMI_COLORSPACE_YUV422:
246*4882a593Smuzhiyun output_format_422 = true;
247*4882a593Smuzhiyun output_format_ycbcr = true;
248*4882a593Smuzhiyun break;
249*4882a593Smuzhiyun default:
250*4882a593Smuzhiyun output_format_422 = false;
251*4882a593Smuzhiyun output_format_ycbcr = false;
252*4882a593Smuzhiyun break;
253*4882a593Smuzhiyun }
254*4882a593Smuzhiyun } else {
255*4882a593Smuzhiyun mode = ADV7511_HDMI_CFG_MODE_DVI;
256*4882a593Smuzhiyun output_format_422 = false;
257*4882a593Smuzhiyun output_format_ycbcr = false;
258*4882a593Smuzhiyun }
259*4882a593Smuzhiyun
260*4882a593Smuzhiyun adv7511_packet_disable(adv7511, ADV7511_PACKET_ENABLE_AVI_INFOFRAME);
261*4882a593Smuzhiyun
262*4882a593Smuzhiyun adv7511_set_colormap(adv7511, config.csc_enable,
263*4882a593Smuzhiyun config.csc_coefficents,
264*4882a593Smuzhiyun config.csc_scaling_factor);
265*4882a593Smuzhiyun
266*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_VIDEO_INPUT_CFG1, 0x81,
267*4882a593Smuzhiyun (output_format_422 << 7) | output_format_ycbcr);
268*4882a593Smuzhiyun
269*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_HDCP_HDMI_CFG,
270*4882a593Smuzhiyun ADV7511_HDMI_CFG_MODE_MASK, mode);
271*4882a593Smuzhiyun
272*4882a593Smuzhiyun hdmi_avi_infoframe_pack(&config.avi_infoframe, infoframe,
273*4882a593Smuzhiyun sizeof(infoframe));
274*4882a593Smuzhiyun
275*4882a593Smuzhiyun /* The AVI infoframe id is not configurable */
276*4882a593Smuzhiyun regmap_bulk_write(adv7511->regmap, ADV7511_REG_AVI_INFOFRAME_VERSION,
277*4882a593Smuzhiyun infoframe + 1, sizeof(infoframe) - 1);
278*4882a593Smuzhiyun
279*4882a593Smuzhiyun adv7511_packet_enable(adv7511, ADV7511_PACKET_ENABLE_AVI_INFOFRAME);
280*4882a593Smuzhiyun }
281*4882a593Smuzhiyun
adv7511_set_link_config(struct adv7511 * adv7511,const struct adv7511_link_config * config)282*4882a593Smuzhiyun static void adv7511_set_link_config(struct adv7511 *adv7511,
283*4882a593Smuzhiyun const struct adv7511_link_config *config)
284*4882a593Smuzhiyun {
285*4882a593Smuzhiyun /*
286*4882a593Smuzhiyun * The input style values documented in the datasheet don't match the
287*4882a593Smuzhiyun * hardware register field values :-(
288*4882a593Smuzhiyun */
289*4882a593Smuzhiyun static const unsigned int input_styles[4] = { 0, 2, 1, 3 };
290*4882a593Smuzhiyun
291*4882a593Smuzhiyun unsigned int clock_delay;
292*4882a593Smuzhiyun unsigned int color_depth;
293*4882a593Smuzhiyun unsigned int input_id;
294*4882a593Smuzhiyun
295*4882a593Smuzhiyun clock_delay = (config->clock_delay + 1200) / 400;
296*4882a593Smuzhiyun color_depth = config->input_color_depth == 8 ? 3
297*4882a593Smuzhiyun : (config->input_color_depth == 10 ? 1 : 2);
298*4882a593Smuzhiyun
299*4882a593Smuzhiyun /* TODO Support input ID 6 */
300*4882a593Smuzhiyun if (config->input_colorspace != HDMI_COLORSPACE_YUV422)
301*4882a593Smuzhiyun input_id = config->input_clock == ADV7511_INPUT_CLOCK_DDR
302*4882a593Smuzhiyun ? 5 : 0;
303*4882a593Smuzhiyun else if (config->input_clock == ADV7511_INPUT_CLOCK_DDR)
304*4882a593Smuzhiyun input_id = config->embedded_sync ? 8 : 7;
305*4882a593Smuzhiyun else if (config->input_clock == ADV7511_INPUT_CLOCK_2X)
306*4882a593Smuzhiyun input_id = config->embedded_sync ? 4 : 3;
307*4882a593Smuzhiyun else
308*4882a593Smuzhiyun input_id = config->embedded_sync ? 2 : 1;
309*4882a593Smuzhiyun
310*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_I2C_FREQ_ID_CFG, 0xf,
311*4882a593Smuzhiyun input_id);
312*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_VIDEO_INPUT_CFG1, 0x7e,
313*4882a593Smuzhiyun (color_depth << 4) |
314*4882a593Smuzhiyun (input_styles[config->input_style] << 2));
315*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_VIDEO_INPUT_CFG2,
316*4882a593Smuzhiyun config->input_justification << 3);
317*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_TIMING_GEN_SEQ,
318*4882a593Smuzhiyun config->sync_pulse << 2);
319*4882a593Smuzhiyun
320*4882a593Smuzhiyun regmap_write(adv7511->regmap, 0xba, clock_delay << 5);
321*4882a593Smuzhiyun
322*4882a593Smuzhiyun adv7511->embedded_sync = config->embedded_sync;
323*4882a593Smuzhiyun adv7511->hsync_polarity = config->hsync_polarity;
324*4882a593Smuzhiyun adv7511->vsync_polarity = config->vsync_polarity;
325*4882a593Smuzhiyun adv7511->rgb = config->input_colorspace == HDMI_COLORSPACE_RGB;
326*4882a593Smuzhiyun }
327*4882a593Smuzhiyun
__adv7511_power_on(struct adv7511 * adv7511)328*4882a593Smuzhiyun static void __adv7511_power_on(struct adv7511 *adv7511)
329*4882a593Smuzhiyun {
330*4882a593Smuzhiyun adv7511->current_edid_segment = -1;
331*4882a593Smuzhiyun
332*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
333*4882a593Smuzhiyun ADV7511_POWER_POWER_DOWN, 0);
334*4882a593Smuzhiyun if (adv7511->i2c_main->irq) {
335*4882a593Smuzhiyun /*
336*4882a593Smuzhiyun * Documentation says the INT_ENABLE registers are reset in
337*4882a593Smuzhiyun * POWER_DOWN mode. My 7511w preserved the bits, however.
338*4882a593Smuzhiyun * Still, let's be safe and stick to the documentation.
339*4882a593Smuzhiyun */
340*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_INT_ENABLE(0),
341*4882a593Smuzhiyun ADV7511_INT0_EDID_READY | ADV7511_INT0_HPD);
342*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap,
343*4882a593Smuzhiyun ADV7511_REG_INT_ENABLE(1),
344*4882a593Smuzhiyun ADV7511_INT1_DDC_ERROR,
345*4882a593Smuzhiyun ADV7511_INT1_DDC_ERROR);
346*4882a593Smuzhiyun }
347*4882a593Smuzhiyun
348*4882a593Smuzhiyun /*
349*4882a593Smuzhiyun * Per spec it is allowed to pulse the HPD signal to indicate that the
350*4882a593Smuzhiyun * EDID information has changed. Some monitors do this when they wakeup
351*4882a593Smuzhiyun * from standby or are enabled. When the HPD goes low the adv7511 is
352*4882a593Smuzhiyun * reset and the outputs are disabled which might cause the monitor to
353*4882a593Smuzhiyun * go to standby again. To avoid this we ignore the HPD pin for the
354*4882a593Smuzhiyun * first few seconds after enabling the output. On the other hand
355*4882a593Smuzhiyun * adv7535 require to enable HPD Override bit for proper HPD.
356*4882a593Smuzhiyun */
357*4882a593Smuzhiyun if (adv7511->type == ADV7535)
358*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2,
359*4882a593Smuzhiyun ADV7535_REG_POWER2_HPD_OVERRIDE,
360*4882a593Smuzhiyun ADV7535_REG_POWER2_HPD_OVERRIDE);
361*4882a593Smuzhiyun else
362*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2,
363*4882a593Smuzhiyun ADV7511_REG_POWER2_HPD_SRC_MASK,
364*4882a593Smuzhiyun ADV7511_REG_POWER2_HPD_SRC_NONE);
365*4882a593Smuzhiyun
366*4882a593Smuzhiyun /* HACK: If we don't delay here edid probing doesn't work properly */
367*4882a593Smuzhiyun msleep(200);
368*4882a593Smuzhiyun }
369*4882a593Smuzhiyun
adv7511_power_on(struct adv7511 * adv7511)370*4882a593Smuzhiyun static void adv7511_power_on(struct adv7511 *adv7511)
371*4882a593Smuzhiyun {
372*4882a593Smuzhiyun __adv7511_power_on(adv7511);
373*4882a593Smuzhiyun
374*4882a593Smuzhiyun /*
375*4882a593Smuzhiyun * Most of the registers are reset during power down or when HPD is low.
376*4882a593Smuzhiyun */
377*4882a593Smuzhiyun regcache_sync(adv7511->regmap);
378*4882a593Smuzhiyun
379*4882a593Smuzhiyun if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
380*4882a593Smuzhiyun adv7533_dsi_power_on(adv7511);
381*4882a593Smuzhiyun adv7511->powered = true;
382*4882a593Smuzhiyun }
383*4882a593Smuzhiyun
__adv7511_power_off(struct adv7511 * adv7511)384*4882a593Smuzhiyun static void __adv7511_power_off(struct adv7511 *adv7511)
385*4882a593Smuzhiyun {
386*4882a593Smuzhiyun /* TODO: setup additional power down modes */
387*4882a593Smuzhiyun if (adv7511->type == ADV7535)
388*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2,
389*4882a593Smuzhiyun ADV7535_REG_POWER2_HPD_OVERRIDE, 0);
390*4882a593Smuzhiyun
391*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER,
392*4882a593Smuzhiyun ADV7511_POWER_POWER_DOWN,
393*4882a593Smuzhiyun ADV7511_POWER_POWER_DOWN);
394*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap,
395*4882a593Smuzhiyun ADV7511_REG_INT_ENABLE(1),
396*4882a593Smuzhiyun ADV7511_INT1_DDC_ERROR, 0);
397*4882a593Smuzhiyun regcache_mark_dirty(adv7511->regmap);
398*4882a593Smuzhiyun }
399*4882a593Smuzhiyun
adv7511_power_off(struct adv7511 * adv7511)400*4882a593Smuzhiyun static void adv7511_power_off(struct adv7511 *adv7511)
401*4882a593Smuzhiyun {
402*4882a593Smuzhiyun __adv7511_power_off(adv7511);
403*4882a593Smuzhiyun if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
404*4882a593Smuzhiyun adv7533_dsi_power_off(adv7511);
405*4882a593Smuzhiyun adv7511->powered = false;
406*4882a593Smuzhiyun }
407*4882a593Smuzhiyun
408*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
409*4882a593Smuzhiyun * Interrupt and hotplug detection
410*4882a593Smuzhiyun */
411*4882a593Smuzhiyun
adv7511_hpd(struct adv7511 * adv7511)412*4882a593Smuzhiyun static bool adv7511_hpd(struct adv7511 *adv7511)
413*4882a593Smuzhiyun {
414*4882a593Smuzhiyun unsigned int irq0;
415*4882a593Smuzhiyun int ret;
416*4882a593Smuzhiyun
417*4882a593Smuzhiyun ret = regmap_read(adv7511->regmap, ADV7511_REG_INT(0), &irq0);
418*4882a593Smuzhiyun if (ret < 0)
419*4882a593Smuzhiyun return false;
420*4882a593Smuzhiyun
421*4882a593Smuzhiyun if (irq0 & ADV7511_INT0_HPD) {
422*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_INT(0),
423*4882a593Smuzhiyun ADV7511_INT0_HPD);
424*4882a593Smuzhiyun return true;
425*4882a593Smuzhiyun }
426*4882a593Smuzhiyun
427*4882a593Smuzhiyun return false;
428*4882a593Smuzhiyun }
429*4882a593Smuzhiyun
adv7511_hpd_work(struct work_struct * work)430*4882a593Smuzhiyun static void adv7511_hpd_work(struct work_struct *work)
431*4882a593Smuzhiyun {
432*4882a593Smuzhiyun struct adv7511 *adv7511 = container_of(work, struct adv7511, hpd_work);
433*4882a593Smuzhiyun enum drm_connector_status status;
434*4882a593Smuzhiyun unsigned int val;
435*4882a593Smuzhiyun int ret;
436*4882a593Smuzhiyun
437*4882a593Smuzhiyun ret = regmap_read(adv7511->regmap, ADV7511_REG_STATUS, &val);
438*4882a593Smuzhiyun if (ret < 0)
439*4882a593Smuzhiyun status = connector_status_disconnected;
440*4882a593Smuzhiyun else if (val & ADV7511_STATUS_HPD)
441*4882a593Smuzhiyun status = connector_status_connected;
442*4882a593Smuzhiyun else
443*4882a593Smuzhiyun status = connector_status_disconnected;
444*4882a593Smuzhiyun
445*4882a593Smuzhiyun /*
446*4882a593Smuzhiyun * The bridge resets its registers on unplug. So when we get a plug
447*4882a593Smuzhiyun * event and we're already supposed to be powered, cycle the bridge to
448*4882a593Smuzhiyun * restore its state.
449*4882a593Smuzhiyun */
450*4882a593Smuzhiyun if (status == connector_status_connected &&
451*4882a593Smuzhiyun adv7511->connector.status == connector_status_disconnected &&
452*4882a593Smuzhiyun adv7511->powered) {
453*4882a593Smuzhiyun regcache_mark_dirty(adv7511->regmap);
454*4882a593Smuzhiyun adv7511_power_on(adv7511);
455*4882a593Smuzhiyun }
456*4882a593Smuzhiyun
457*4882a593Smuzhiyun if (adv7511->connector.status != status) {
458*4882a593Smuzhiyun adv7511->connector.status = status;
459*4882a593Smuzhiyun
460*4882a593Smuzhiyun if (adv7511->connector.dev) {
461*4882a593Smuzhiyun if (status == connector_status_disconnected)
462*4882a593Smuzhiyun cec_phys_addr_invalidate(adv7511->cec_adap);
463*4882a593Smuzhiyun drm_kms_helper_hotplug_event(adv7511->connector.dev);
464*4882a593Smuzhiyun } else {
465*4882a593Smuzhiyun drm_bridge_hpd_notify(&adv7511->bridge, status);
466*4882a593Smuzhiyun }
467*4882a593Smuzhiyun }
468*4882a593Smuzhiyun }
469*4882a593Smuzhiyun
adv7511_irq_process(struct adv7511 * adv7511,bool process_hpd)470*4882a593Smuzhiyun static int adv7511_irq_process(struct adv7511 *adv7511, bool process_hpd)
471*4882a593Smuzhiyun {
472*4882a593Smuzhiyun unsigned int irq0, irq1;
473*4882a593Smuzhiyun int ret;
474*4882a593Smuzhiyun
475*4882a593Smuzhiyun ret = regmap_read(adv7511->regmap, ADV7511_REG_INT(0), &irq0);
476*4882a593Smuzhiyun if (ret < 0)
477*4882a593Smuzhiyun return ret;
478*4882a593Smuzhiyun
479*4882a593Smuzhiyun ret = regmap_read(adv7511->regmap, ADV7511_REG_INT(1), &irq1);
480*4882a593Smuzhiyun if (ret < 0)
481*4882a593Smuzhiyun return ret;
482*4882a593Smuzhiyun
483*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_INT(0), irq0);
484*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_INT(1), irq1);
485*4882a593Smuzhiyun
486*4882a593Smuzhiyun if (process_hpd && irq0 & ADV7511_INT0_HPD && adv7511->bridge.encoder)
487*4882a593Smuzhiyun schedule_work(&adv7511->hpd_work);
488*4882a593Smuzhiyun
489*4882a593Smuzhiyun if (irq0 & ADV7511_INT0_EDID_READY || irq1 & ADV7511_INT1_DDC_ERROR) {
490*4882a593Smuzhiyun adv7511->edid_read = true;
491*4882a593Smuzhiyun
492*4882a593Smuzhiyun if (adv7511->i2c_main->irq)
493*4882a593Smuzhiyun wake_up_all(&adv7511->wq);
494*4882a593Smuzhiyun }
495*4882a593Smuzhiyun
496*4882a593Smuzhiyun #ifdef CONFIG_DRM_I2C_ADV7511_CEC
497*4882a593Smuzhiyun adv7511_cec_irq_process(adv7511, irq1);
498*4882a593Smuzhiyun #endif
499*4882a593Smuzhiyun
500*4882a593Smuzhiyun return 0;
501*4882a593Smuzhiyun }
502*4882a593Smuzhiyun
adv7511_irq_handler(int irq,void * devid)503*4882a593Smuzhiyun static irqreturn_t adv7511_irq_handler(int irq, void *devid)
504*4882a593Smuzhiyun {
505*4882a593Smuzhiyun struct adv7511 *adv7511 = devid;
506*4882a593Smuzhiyun int ret;
507*4882a593Smuzhiyun
508*4882a593Smuzhiyun ret = adv7511_irq_process(adv7511, true);
509*4882a593Smuzhiyun return ret < 0 ? IRQ_NONE : IRQ_HANDLED;
510*4882a593Smuzhiyun }
511*4882a593Smuzhiyun
512*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
513*4882a593Smuzhiyun * EDID retrieval
514*4882a593Smuzhiyun */
515*4882a593Smuzhiyun
adv7511_wait_for_edid(struct adv7511 * adv7511,int timeout)516*4882a593Smuzhiyun static int adv7511_wait_for_edid(struct adv7511 *adv7511, int timeout)
517*4882a593Smuzhiyun {
518*4882a593Smuzhiyun int ret;
519*4882a593Smuzhiyun
520*4882a593Smuzhiyun if (adv7511->i2c_main->irq) {
521*4882a593Smuzhiyun ret = wait_event_interruptible_timeout(adv7511->wq,
522*4882a593Smuzhiyun adv7511->edid_read, msecs_to_jiffies(timeout));
523*4882a593Smuzhiyun } else {
524*4882a593Smuzhiyun for (; timeout > 0; timeout -= 25) {
525*4882a593Smuzhiyun ret = adv7511_irq_process(adv7511, false);
526*4882a593Smuzhiyun if (ret < 0)
527*4882a593Smuzhiyun break;
528*4882a593Smuzhiyun
529*4882a593Smuzhiyun if (adv7511->edid_read)
530*4882a593Smuzhiyun break;
531*4882a593Smuzhiyun
532*4882a593Smuzhiyun msleep(25);
533*4882a593Smuzhiyun }
534*4882a593Smuzhiyun }
535*4882a593Smuzhiyun
536*4882a593Smuzhiyun return adv7511->edid_read ? 0 : -EIO;
537*4882a593Smuzhiyun }
538*4882a593Smuzhiyun
adv7511_get_edid_block(void * data,u8 * buf,unsigned int block,size_t len)539*4882a593Smuzhiyun static int adv7511_get_edid_block(void *data, u8 *buf, unsigned int block,
540*4882a593Smuzhiyun size_t len)
541*4882a593Smuzhiyun {
542*4882a593Smuzhiyun struct adv7511 *adv7511 = data;
543*4882a593Smuzhiyun struct i2c_msg xfer[2];
544*4882a593Smuzhiyun uint8_t offset;
545*4882a593Smuzhiyun unsigned int i;
546*4882a593Smuzhiyun int ret;
547*4882a593Smuzhiyun
548*4882a593Smuzhiyun if (len > 128)
549*4882a593Smuzhiyun return -EINVAL;
550*4882a593Smuzhiyun
551*4882a593Smuzhiyun if (adv7511->current_edid_segment != block / 2) {
552*4882a593Smuzhiyun unsigned int status;
553*4882a593Smuzhiyun
554*4882a593Smuzhiyun ret = regmap_read(adv7511->regmap, ADV7511_REG_DDC_STATUS,
555*4882a593Smuzhiyun &status);
556*4882a593Smuzhiyun if (ret < 0)
557*4882a593Smuzhiyun return ret;
558*4882a593Smuzhiyun
559*4882a593Smuzhiyun if (status != 2) {
560*4882a593Smuzhiyun adv7511->edid_read = false;
561*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_EDID_SEGMENT,
562*4882a593Smuzhiyun block);
563*4882a593Smuzhiyun ret = adv7511_wait_for_edid(adv7511, 200);
564*4882a593Smuzhiyun if (ret < 0)
565*4882a593Smuzhiyun return ret;
566*4882a593Smuzhiyun }
567*4882a593Smuzhiyun
568*4882a593Smuzhiyun /* Break this apart, hopefully more I2C controllers will
569*4882a593Smuzhiyun * support 64 byte transfers than 256 byte transfers
570*4882a593Smuzhiyun */
571*4882a593Smuzhiyun
572*4882a593Smuzhiyun xfer[0].addr = adv7511->i2c_edid->addr;
573*4882a593Smuzhiyun xfer[0].flags = 0;
574*4882a593Smuzhiyun xfer[0].len = 1;
575*4882a593Smuzhiyun xfer[0].buf = &offset;
576*4882a593Smuzhiyun xfer[1].addr = adv7511->i2c_edid->addr;
577*4882a593Smuzhiyun xfer[1].flags = I2C_M_RD;
578*4882a593Smuzhiyun xfer[1].len = 64;
579*4882a593Smuzhiyun xfer[1].buf = adv7511->edid_buf;
580*4882a593Smuzhiyun
581*4882a593Smuzhiyun offset = 0;
582*4882a593Smuzhiyun
583*4882a593Smuzhiyun for (i = 0; i < 4; ++i) {
584*4882a593Smuzhiyun ret = i2c_transfer(adv7511->i2c_edid->adapter, xfer,
585*4882a593Smuzhiyun ARRAY_SIZE(xfer));
586*4882a593Smuzhiyun if (ret < 0)
587*4882a593Smuzhiyun return ret;
588*4882a593Smuzhiyun else if (ret != 2)
589*4882a593Smuzhiyun return -EIO;
590*4882a593Smuzhiyun
591*4882a593Smuzhiyun xfer[1].buf += 64;
592*4882a593Smuzhiyun offset += 64;
593*4882a593Smuzhiyun }
594*4882a593Smuzhiyun
595*4882a593Smuzhiyun adv7511->current_edid_segment = block / 2;
596*4882a593Smuzhiyun }
597*4882a593Smuzhiyun
598*4882a593Smuzhiyun if (block % 2 == 0)
599*4882a593Smuzhiyun memcpy(buf, adv7511->edid_buf, len);
600*4882a593Smuzhiyun else
601*4882a593Smuzhiyun memcpy(buf, adv7511->edid_buf + 128, len);
602*4882a593Smuzhiyun
603*4882a593Smuzhiyun return 0;
604*4882a593Smuzhiyun }
605*4882a593Smuzhiyun
606*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
607*4882a593Smuzhiyun * ADV75xx helpers
608*4882a593Smuzhiyun */
609*4882a593Smuzhiyun
adv7511_get_edid(struct adv7511 * adv7511,struct drm_connector * connector)610*4882a593Smuzhiyun static struct edid *adv7511_get_edid(struct adv7511 *adv7511,
611*4882a593Smuzhiyun struct drm_connector *connector)
612*4882a593Smuzhiyun {
613*4882a593Smuzhiyun struct edid *edid;
614*4882a593Smuzhiyun
615*4882a593Smuzhiyun /* Reading the EDID only works if the device is powered */
616*4882a593Smuzhiyun if (!adv7511->powered) {
617*4882a593Smuzhiyun unsigned int edid_i2c_addr =
618*4882a593Smuzhiyun (adv7511->i2c_edid->addr << 1);
619*4882a593Smuzhiyun
620*4882a593Smuzhiyun __adv7511_power_on(adv7511);
621*4882a593Smuzhiyun
622*4882a593Smuzhiyun /* Reset the EDID_I2C_ADDR register as it might be cleared */
623*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR,
624*4882a593Smuzhiyun edid_i2c_addr);
625*4882a593Smuzhiyun }
626*4882a593Smuzhiyun
627*4882a593Smuzhiyun edid = drm_do_get_edid(connector, adv7511_get_edid_block, adv7511);
628*4882a593Smuzhiyun
629*4882a593Smuzhiyun if (!adv7511->powered)
630*4882a593Smuzhiyun __adv7511_power_off(adv7511);
631*4882a593Smuzhiyun
632*4882a593Smuzhiyun adv7511_set_config_csc(adv7511, connector, adv7511->rgb,
633*4882a593Smuzhiyun drm_detect_hdmi_monitor(edid));
634*4882a593Smuzhiyun
635*4882a593Smuzhiyun cec_s_phys_addr_from_edid(adv7511->cec_adap, edid);
636*4882a593Smuzhiyun
637*4882a593Smuzhiyun return edid;
638*4882a593Smuzhiyun }
639*4882a593Smuzhiyun
adv7511_get_modes(struct adv7511 * adv7511,struct drm_connector * connector)640*4882a593Smuzhiyun static int adv7511_get_modes(struct adv7511 *adv7511,
641*4882a593Smuzhiyun struct drm_connector *connector)
642*4882a593Smuzhiyun {
643*4882a593Smuzhiyun struct edid *edid;
644*4882a593Smuzhiyun unsigned int count;
645*4882a593Smuzhiyun
646*4882a593Smuzhiyun edid = adv7511_get_edid(adv7511, connector);
647*4882a593Smuzhiyun
648*4882a593Smuzhiyun drm_connector_update_edid_property(connector, edid);
649*4882a593Smuzhiyun count = drm_add_edid_modes(connector, edid);
650*4882a593Smuzhiyun
651*4882a593Smuzhiyun kfree(edid);
652*4882a593Smuzhiyun
653*4882a593Smuzhiyun return count;
654*4882a593Smuzhiyun }
655*4882a593Smuzhiyun
656*4882a593Smuzhiyun static enum drm_connector_status
adv7511_detect(struct adv7511 * adv7511,struct drm_connector * connector)657*4882a593Smuzhiyun adv7511_detect(struct adv7511 *adv7511, struct drm_connector *connector)
658*4882a593Smuzhiyun {
659*4882a593Smuzhiyun enum drm_connector_status status;
660*4882a593Smuzhiyun unsigned int val;
661*4882a593Smuzhiyun bool hpd;
662*4882a593Smuzhiyun int ret;
663*4882a593Smuzhiyun
664*4882a593Smuzhiyun ret = regmap_read(adv7511->regmap, ADV7511_REG_STATUS, &val);
665*4882a593Smuzhiyun if (ret < 0)
666*4882a593Smuzhiyun return connector_status_disconnected;
667*4882a593Smuzhiyun
668*4882a593Smuzhiyun if (val & ADV7511_STATUS_HPD)
669*4882a593Smuzhiyun status = connector_status_connected;
670*4882a593Smuzhiyun else
671*4882a593Smuzhiyun status = connector_status_disconnected;
672*4882a593Smuzhiyun
673*4882a593Smuzhiyun hpd = adv7511_hpd(adv7511);
674*4882a593Smuzhiyun
675*4882a593Smuzhiyun /* The chip resets itself when the cable is disconnected, so in case
676*4882a593Smuzhiyun * there is a pending HPD interrupt and the cable is connected there was
677*4882a593Smuzhiyun * at least one transition from disconnected to connected and the chip
678*4882a593Smuzhiyun * has to be reinitialized. */
679*4882a593Smuzhiyun if (status == connector_status_connected && hpd && adv7511->powered) {
680*4882a593Smuzhiyun regcache_mark_dirty(adv7511->regmap);
681*4882a593Smuzhiyun adv7511_power_on(adv7511);
682*4882a593Smuzhiyun if (connector)
683*4882a593Smuzhiyun adv7511_get_modes(adv7511, connector);
684*4882a593Smuzhiyun if (adv7511->status == connector_status_connected)
685*4882a593Smuzhiyun status = connector_status_disconnected;
686*4882a593Smuzhiyun } else {
687*4882a593Smuzhiyun /* Renable HPD sensing */
688*4882a593Smuzhiyun if (adv7511->type == ADV7535)
689*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2,
690*4882a593Smuzhiyun ADV7535_REG_POWER2_HPD_OVERRIDE,
691*4882a593Smuzhiyun ADV7535_REG_POWER2_HPD_OVERRIDE);
692*4882a593Smuzhiyun else
693*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, ADV7511_REG_POWER2,
694*4882a593Smuzhiyun ADV7511_REG_POWER2_HPD_SRC_MASK,
695*4882a593Smuzhiyun ADV7511_REG_POWER2_HPD_SRC_BOTH);
696*4882a593Smuzhiyun }
697*4882a593Smuzhiyun
698*4882a593Smuzhiyun adv7511->status = status;
699*4882a593Smuzhiyun return status;
700*4882a593Smuzhiyun }
701*4882a593Smuzhiyun
adv7511_mode_valid(struct adv7511 * adv7511,struct drm_display_mode * mode)702*4882a593Smuzhiyun static enum drm_mode_status adv7511_mode_valid(struct adv7511 *adv7511,
703*4882a593Smuzhiyun struct drm_display_mode *mode)
704*4882a593Smuzhiyun {
705*4882a593Smuzhiyun if (mode->clock > 165000)
706*4882a593Smuzhiyun return MODE_CLOCK_HIGH;
707*4882a593Smuzhiyun
708*4882a593Smuzhiyun return MODE_OK;
709*4882a593Smuzhiyun }
710*4882a593Smuzhiyun
adv7511_mode_set(struct adv7511 * adv7511,const struct drm_display_mode * mode,const struct drm_display_mode * adj_mode)711*4882a593Smuzhiyun static void adv7511_mode_set(struct adv7511 *adv7511,
712*4882a593Smuzhiyun const struct drm_display_mode *mode,
713*4882a593Smuzhiyun const struct drm_display_mode *adj_mode)
714*4882a593Smuzhiyun {
715*4882a593Smuzhiyun unsigned int low_refresh_rate;
716*4882a593Smuzhiyun unsigned int hsync_polarity = 0;
717*4882a593Smuzhiyun unsigned int vsync_polarity = 0;
718*4882a593Smuzhiyun
719*4882a593Smuzhiyun if (adv7511->embedded_sync) {
720*4882a593Smuzhiyun unsigned int hsync_offset, hsync_len;
721*4882a593Smuzhiyun unsigned int vsync_offset, vsync_len;
722*4882a593Smuzhiyun
723*4882a593Smuzhiyun hsync_offset = adj_mode->crtc_hsync_start -
724*4882a593Smuzhiyun adj_mode->crtc_hdisplay;
725*4882a593Smuzhiyun vsync_offset = adj_mode->crtc_vsync_start -
726*4882a593Smuzhiyun adj_mode->crtc_vdisplay;
727*4882a593Smuzhiyun hsync_len = adj_mode->crtc_hsync_end -
728*4882a593Smuzhiyun adj_mode->crtc_hsync_start;
729*4882a593Smuzhiyun vsync_len = adj_mode->crtc_vsync_end -
730*4882a593Smuzhiyun adj_mode->crtc_vsync_start;
731*4882a593Smuzhiyun
732*4882a593Smuzhiyun /* The hardware vsync generator has a off-by-one bug */
733*4882a593Smuzhiyun vsync_offset += 1;
734*4882a593Smuzhiyun
735*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_HSYNC_PLACEMENT_MSB,
736*4882a593Smuzhiyun ((hsync_offset >> 10) & 0x7) << 5);
737*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(0),
738*4882a593Smuzhiyun (hsync_offset >> 2) & 0xff);
739*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(1),
740*4882a593Smuzhiyun ((hsync_offset & 0x3) << 6) |
741*4882a593Smuzhiyun ((hsync_len >> 4) & 0x3f));
742*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(2),
743*4882a593Smuzhiyun ((hsync_len & 0xf) << 4) |
744*4882a593Smuzhiyun ((vsync_offset >> 6) & 0xf));
745*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(3),
746*4882a593Smuzhiyun ((vsync_offset & 0x3f) << 2) |
747*4882a593Smuzhiyun ((vsync_len >> 8) & 0x3));
748*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_SYNC_DECODER(4),
749*4882a593Smuzhiyun vsync_len & 0xff);
750*4882a593Smuzhiyun
751*4882a593Smuzhiyun hsync_polarity = !(adj_mode->flags & DRM_MODE_FLAG_PHSYNC);
752*4882a593Smuzhiyun vsync_polarity = !(adj_mode->flags & DRM_MODE_FLAG_PVSYNC);
753*4882a593Smuzhiyun } else {
754*4882a593Smuzhiyun enum adv7511_sync_polarity mode_hsync_polarity;
755*4882a593Smuzhiyun enum adv7511_sync_polarity mode_vsync_polarity;
756*4882a593Smuzhiyun
757*4882a593Smuzhiyun /**
758*4882a593Smuzhiyun * If the input signal is always low or always high we want to
759*4882a593Smuzhiyun * invert or let it passthrough depending on the polarity of the
760*4882a593Smuzhiyun * current mode.
761*4882a593Smuzhiyun **/
762*4882a593Smuzhiyun if (adj_mode->flags & DRM_MODE_FLAG_NHSYNC)
763*4882a593Smuzhiyun mode_hsync_polarity = ADV7511_SYNC_POLARITY_LOW;
764*4882a593Smuzhiyun else
765*4882a593Smuzhiyun mode_hsync_polarity = ADV7511_SYNC_POLARITY_HIGH;
766*4882a593Smuzhiyun
767*4882a593Smuzhiyun if (adj_mode->flags & DRM_MODE_FLAG_NVSYNC)
768*4882a593Smuzhiyun mode_vsync_polarity = ADV7511_SYNC_POLARITY_LOW;
769*4882a593Smuzhiyun else
770*4882a593Smuzhiyun mode_vsync_polarity = ADV7511_SYNC_POLARITY_HIGH;
771*4882a593Smuzhiyun
772*4882a593Smuzhiyun if (adv7511->hsync_polarity != mode_hsync_polarity &&
773*4882a593Smuzhiyun adv7511->hsync_polarity !=
774*4882a593Smuzhiyun ADV7511_SYNC_POLARITY_PASSTHROUGH)
775*4882a593Smuzhiyun hsync_polarity = 1;
776*4882a593Smuzhiyun
777*4882a593Smuzhiyun if (adv7511->vsync_polarity != mode_vsync_polarity &&
778*4882a593Smuzhiyun adv7511->vsync_polarity !=
779*4882a593Smuzhiyun ADV7511_SYNC_POLARITY_PASSTHROUGH)
780*4882a593Smuzhiyun vsync_polarity = 1;
781*4882a593Smuzhiyun }
782*4882a593Smuzhiyun
783*4882a593Smuzhiyun if (drm_mode_vrefresh(mode) <= 24)
784*4882a593Smuzhiyun low_refresh_rate = ADV7511_LOW_REFRESH_RATE_24HZ;
785*4882a593Smuzhiyun else if (drm_mode_vrefresh(mode) <= 25)
786*4882a593Smuzhiyun low_refresh_rate = ADV7511_LOW_REFRESH_RATE_25HZ;
787*4882a593Smuzhiyun else if (drm_mode_vrefresh(mode) <= 30)
788*4882a593Smuzhiyun low_refresh_rate = ADV7511_LOW_REFRESH_RATE_30HZ;
789*4882a593Smuzhiyun else
790*4882a593Smuzhiyun low_refresh_rate = ADV7511_LOW_REFRESH_RATE_NONE;
791*4882a593Smuzhiyun
792*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, 0xfb,
793*4882a593Smuzhiyun 0x6, low_refresh_rate << 1);
794*4882a593Smuzhiyun regmap_update_bits(adv7511->regmap, 0x17,
795*4882a593Smuzhiyun 0x60, (vsync_polarity << 6) | (hsync_polarity << 5));
796*4882a593Smuzhiyun
797*4882a593Smuzhiyun if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
798*4882a593Smuzhiyun adv7533_mode_set(adv7511, adj_mode);
799*4882a593Smuzhiyun
800*4882a593Smuzhiyun drm_mode_copy(&adv7511->curr_mode, adj_mode);
801*4882a593Smuzhiyun
802*4882a593Smuzhiyun /*
803*4882a593Smuzhiyun * TODO Test first order 4:2:2 to 4:4:4 up conversion method, which is
804*4882a593Smuzhiyun * supposed to give better results.
805*4882a593Smuzhiyun */
806*4882a593Smuzhiyun
807*4882a593Smuzhiyun adv7511->f_tmds = mode->clock;
808*4882a593Smuzhiyun }
809*4882a593Smuzhiyun
810*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
811*4882a593Smuzhiyun * DRM Connector Operations
812*4882a593Smuzhiyun */
813*4882a593Smuzhiyun
connector_to_adv7511(struct drm_connector * connector)814*4882a593Smuzhiyun static struct adv7511 *connector_to_adv7511(struct drm_connector *connector)
815*4882a593Smuzhiyun {
816*4882a593Smuzhiyun return container_of(connector, struct adv7511, connector);
817*4882a593Smuzhiyun }
818*4882a593Smuzhiyun
adv7511_connector_get_modes(struct drm_connector * connector)819*4882a593Smuzhiyun static int adv7511_connector_get_modes(struct drm_connector *connector)
820*4882a593Smuzhiyun {
821*4882a593Smuzhiyun struct adv7511 *adv = connector_to_adv7511(connector);
822*4882a593Smuzhiyun
823*4882a593Smuzhiyun return adv7511_get_modes(adv, connector);
824*4882a593Smuzhiyun }
825*4882a593Smuzhiyun
826*4882a593Smuzhiyun static enum drm_mode_status
adv7511_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)827*4882a593Smuzhiyun adv7511_connector_mode_valid(struct drm_connector *connector,
828*4882a593Smuzhiyun struct drm_display_mode *mode)
829*4882a593Smuzhiyun {
830*4882a593Smuzhiyun struct adv7511 *adv = connector_to_adv7511(connector);
831*4882a593Smuzhiyun
832*4882a593Smuzhiyun return adv7511_mode_valid(adv, mode);
833*4882a593Smuzhiyun }
834*4882a593Smuzhiyun
835*4882a593Smuzhiyun static struct drm_connector_helper_funcs adv7511_connector_helper_funcs = {
836*4882a593Smuzhiyun .get_modes = adv7511_connector_get_modes,
837*4882a593Smuzhiyun .mode_valid = adv7511_connector_mode_valid,
838*4882a593Smuzhiyun };
839*4882a593Smuzhiyun
840*4882a593Smuzhiyun static enum drm_connector_status
adv7511_connector_detect(struct drm_connector * connector,bool force)841*4882a593Smuzhiyun adv7511_connector_detect(struct drm_connector *connector, bool force)
842*4882a593Smuzhiyun {
843*4882a593Smuzhiyun struct adv7511 *adv = connector_to_adv7511(connector);
844*4882a593Smuzhiyun
845*4882a593Smuzhiyun return adv7511_detect(adv, connector);
846*4882a593Smuzhiyun }
847*4882a593Smuzhiyun
848*4882a593Smuzhiyun static const struct drm_connector_funcs adv7511_connector_funcs = {
849*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
850*4882a593Smuzhiyun .detect = adv7511_connector_detect,
851*4882a593Smuzhiyun .destroy = drm_connector_cleanup,
852*4882a593Smuzhiyun .reset = drm_atomic_helper_connector_reset,
853*4882a593Smuzhiyun .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
854*4882a593Smuzhiyun .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
855*4882a593Smuzhiyun };
856*4882a593Smuzhiyun
adv7511_connector_init(struct adv7511 * adv)857*4882a593Smuzhiyun static int adv7511_connector_init(struct adv7511 *adv)
858*4882a593Smuzhiyun {
859*4882a593Smuzhiyun struct drm_bridge *bridge = &adv->bridge;
860*4882a593Smuzhiyun int ret;
861*4882a593Smuzhiyun
862*4882a593Smuzhiyun if (!bridge->encoder) {
863*4882a593Smuzhiyun DRM_ERROR("Parent encoder object not found");
864*4882a593Smuzhiyun return -ENODEV;
865*4882a593Smuzhiyun }
866*4882a593Smuzhiyun
867*4882a593Smuzhiyun if (adv->i2c_main->irq)
868*4882a593Smuzhiyun adv->connector.polled = DRM_CONNECTOR_POLL_HPD;
869*4882a593Smuzhiyun else
870*4882a593Smuzhiyun adv->connector.polled = DRM_CONNECTOR_POLL_CONNECT |
871*4882a593Smuzhiyun DRM_CONNECTOR_POLL_DISCONNECT;
872*4882a593Smuzhiyun
873*4882a593Smuzhiyun ret = drm_connector_init(bridge->dev, &adv->connector,
874*4882a593Smuzhiyun &adv7511_connector_funcs,
875*4882a593Smuzhiyun DRM_MODE_CONNECTOR_HDMIA);
876*4882a593Smuzhiyun if (ret < 0) {
877*4882a593Smuzhiyun DRM_ERROR("Failed to initialize connector with drm\n");
878*4882a593Smuzhiyun return ret;
879*4882a593Smuzhiyun }
880*4882a593Smuzhiyun drm_connector_helper_add(&adv->connector,
881*4882a593Smuzhiyun &adv7511_connector_helper_funcs);
882*4882a593Smuzhiyun drm_connector_attach_encoder(&adv->connector, bridge->encoder);
883*4882a593Smuzhiyun
884*4882a593Smuzhiyun return 0;
885*4882a593Smuzhiyun }
886*4882a593Smuzhiyun
887*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
888*4882a593Smuzhiyun * DRM Bridge Operations
889*4882a593Smuzhiyun */
890*4882a593Smuzhiyun
bridge_to_adv7511(struct drm_bridge * bridge)891*4882a593Smuzhiyun static struct adv7511 *bridge_to_adv7511(struct drm_bridge *bridge)
892*4882a593Smuzhiyun {
893*4882a593Smuzhiyun return container_of(bridge, struct adv7511, bridge);
894*4882a593Smuzhiyun }
895*4882a593Smuzhiyun
adv7511_bridge_enable(struct drm_bridge * bridge)896*4882a593Smuzhiyun static void adv7511_bridge_enable(struct drm_bridge *bridge)
897*4882a593Smuzhiyun {
898*4882a593Smuzhiyun struct adv7511 *adv = bridge_to_adv7511(bridge);
899*4882a593Smuzhiyun
900*4882a593Smuzhiyun adv7511_power_on(adv);
901*4882a593Smuzhiyun }
902*4882a593Smuzhiyun
adv7511_bridge_disable(struct drm_bridge * bridge)903*4882a593Smuzhiyun static void adv7511_bridge_disable(struct drm_bridge *bridge)
904*4882a593Smuzhiyun {
905*4882a593Smuzhiyun struct adv7511 *adv = bridge_to_adv7511(bridge);
906*4882a593Smuzhiyun
907*4882a593Smuzhiyun adv7511_power_off(adv);
908*4882a593Smuzhiyun }
909*4882a593Smuzhiyun
adv7511_bridge_mode_set(struct drm_bridge * bridge,const struct drm_display_mode * mode,const struct drm_display_mode * adj_mode)910*4882a593Smuzhiyun static void adv7511_bridge_mode_set(struct drm_bridge *bridge,
911*4882a593Smuzhiyun const struct drm_display_mode *mode,
912*4882a593Smuzhiyun const struct drm_display_mode *adj_mode)
913*4882a593Smuzhiyun {
914*4882a593Smuzhiyun struct adv7511 *adv = bridge_to_adv7511(bridge);
915*4882a593Smuzhiyun
916*4882a593Smuzhiyun adv7511_mode_set(adv, mode, adj_mode);
917*4882a593Smuzhiyun }
918*4882a593Smuzhiyun
adv7511_bridge_attach(struct drm_bridge * bridge,enum drm_bridge_attach_flags flags)919*4882a593Smuzhiyun static int adv7511_bridge_attach(struct drm_bridge *bridge,
920*4882a593Smuzhiyun enum drm_bridge_attach_flags flags)
921*4882a593Smuzhiyun {
922*4882a593Smuzhiyun struct adv7511 *adv = bridge_to_adv7511(bridge);
923*4882a593Smuzhiyun int ret = 0;
924*4882a593Smuzhiyun
925*4882a593Smuzhiyun if (!(flags & DRM_BRIDGE_ATTACH_NO_CONNECTOR)) {
926*4882a593Smuzhiyun ret = adv7511_connector_init(adv);
927*4882a593Smuzhiyun if (ret < 0)
928*4882a593Smuzhiyun return ret;
929*4882a593Smuzhiyun }
930*4882a593Smuzhiyun
931*4882a593Smuzhiyun if (adv->type == ADV7533 || adv->type == ADV7535)
932*4882a593Smuzhiyun ret = adv7533_attach_dsi(adv);
933*4882a593Smuzhiyun
934*4882a593Smuzhiyun if (adv->i2c_main->irq)
935*4882a593Smuzhiyun regmap_write(adv->regmap, ADV7511_REG_INT_ENABLE(0),
936*4882a593Smuzhiyun ADV7511_INT0_HPD);
937*4882a593Smuzhiyun
938*4882a593Smuzhiyun return ret;
939*4882a593Smuzhiyun }
940*4882a593Smuzhiyun
adv7511_bridge_detect(struct drm_bridge * bridge)941*4882a593Smuzhiyun static enum drm_connector_status adv7511_bridge_detect(struct drm_bridge *bridge)
942*4882a593Smuzhiyun {
943*4882a593Smuzhiyun struct adv7511 *adv = bridge_to_adv7511(bridge);
944*4882a593Smuzhiyun
945*4882a593Smuzhiyun return adv7511_detect(adv, NULL);
946*4882a593Smuzhiyun }
947*4882a593Smuzhiyun
adv7511_bridge_get_edid(struct drm_bridge * bridge,struct drm_connector * connector)948*4882a593Smuzhiyun static struct edid *adv7511_bridge_get_edid(struct drm_bridge *bridge,
949*4882a593Smuzhiyun struct drm_connector *connector)
950*4882a593Smuzhiyun {
951*4882a593Smuzhiyun struct adv7511 *adv = bridge_to_adv7511(bridge);
952*4882a593Smuzhiyun
953*4882a593Smuzhiyun return adv7511_get_edid(adv, connector);
954*4882a593Smuzhiyun }
955*4882a593Smuzhiyun
adv7511_bridge_hpd_notify(struct drm_bridge * bridge,enum drm_connector_status status)956*4882a593Smuzhiyun static void adv7511_bridge_hpd_notify(struct drm_bridge *bridge,
957*4882a593Smuzhiyun enum drm_connector_status status)
958*4882a593Smuzhiyun {
959*4882a593Smuzhiyun struct adv7511 *adv = bridge_to_adv7511(bridge);
960*4882a593Smuzhiyun
961*4882a593Smuzhiyun if (status == connector_status_disconnected)
962*4882a593Smuzhiyun cec_phys_addr_invalidate(adv->cec_adap);
963*4882a593Smuzhiyun }
964*4882a593Smuzhiyun
965*4882a593Smuzhiyun static const struct drm_bridge_funcs adv7511_bridge_funcs = {
966*4882a593Smuzhiyun .enable = adv7511_bridge_enable,
967*4882a593Smuzhiyun .disable = adv7511_bridge_disable,
968*4882a593Smuzhiyun .mode_set = adv7511_bridge_mode_set,
969*4882a593Smuzhiyun .attach = adv7511_bridge_attach,
970*4882a593Smuzhiyun .detect = adv7511_bridge_detect,
971*4882a593Smuzhiyun .get_edid = adv7511_bridge_get_edid,
972*4882a593Smuzhiyun .hpd_notify = adv7511_bridge_hpd_notify,
973*4882a593Smuzhiyun };
974*4882a593Smuzhiyun
975*4882a593Smuzhiyun /* -----------------------------------------------------------------------------
976*4882a593Smuzhiyun * Probe & remove
977*4882a593Smuzhiyun */
978*4882a593Smuzhiyun
979*4882a593Smuzhiyun static const char * const adv7511_supply_names[] = {
980*4882a593Smuzhiyun "avdd",
981*4882a593Smuzhiyun "dvdd",
982*4882a593Smuzhiyun "pvdd",
983*4882a593Smuzhiyun "bgvdd",
984*4882a593Smuzhiyun "dvdd-3v",
985*4882a593Smuzhiyun };
986*4882a593Smuzhiyun
987*4882a593Smuzhiyun static const char * const adv7533_supply_names[] = {
988*4882a593Smuzhiyun "avdd",
989*4882a593Smuzhiyun "dvdd",
990*4882a593Smuzhiyun "pvdd",
991*4882a593Smuzhiyun "a2vdd",
992*4882a593Smuzhiyun "v3p3",
993*4882a593Smuzhiyun "v1p2",
994*4882a593Smuzhiyun };
995*4882a593Smuzhiyun
adv7511_init_regulators(struct adv7511 * adv)996*4882a593Smuzhiyun static int adv7511_init_regulators(struct adv7511 *adv)
997*4882a593Smuzhiyun {
998*4882a593Smuzhiyun struct device *dev = &adv->i2c_main->dev;
999*4882a593Smuzhiyun const char * const *supply_names;
1000*4882a593Smuzhiyun unsigned int i;
1001*4882a593Smuzhiyun int ret;
1002*4882a593Smuzhiyun
1003*4882a593Smuzhiyun if (adv->type == ADV7511) {
1004*4882a593Smuzhiyun supply_names = adv7511_supply_names;
1005*4882a593Smuzhiyun adv->num_supplies = ARRAY_SIZE(adv7511_supply_names);
1006*4882a593Smuzhiyun } else {
1007*4882a593Smuzhiyun supply_names = adv7533_supply_names;
1008*4882a593Smuzhiyun adv->num_supplies = ARRAY_SIZE(adv7533_supply_names);
1009*4882a593Smuzhiyun }
1010*4882a593Smuzhiyun
1011*4882a593Smuzhiyun adv->supplies = devm_kcalloc(dev, adv->num_supplies,
1012*4882a593Smuzhiyun sizeof(*adv->supplies), GFP_KERNEL);
1013*4882a593Smuzhiyun if (!adv->supplies)
1014*4882a593Smuzhiyun return -ENOMEM;
1015*4882a593Smuzhiyun
1016*4882a593Smuzhiyun for (i = 0; i < adv->num_supplies; i++)
1017*4882a593Smuzhiyun adv->supplies[i].supply = supply_names[i];
1018*4882a593Smuzhiyun
1019*4882a593Smuzhiyun ret = devm_regulator_bulk_get(dev, adv->num_supplies, adv->supplies);
1020*4882a593Smuzhiyun if (ret)
1021*4882a593Smuzhiyun return ret;
1022*4882a593Smuzhiyun
1023*4882a593Smuzhiyun return regulator_bulk_enable(adv->num_supplies, adv->supplies);
1024*4882a593Smuzhiyun }
1025*4882a593Smuzhiyun
adv7511_uninit_regulators(struct adv7511 * adv)1026*4882a593Smuzhiyun static void adv7511_uninit_regulators(struct adv7511 *adv)
1027*4882a593Smuzhiyun {
1028*4882a593Smuzhiyun regulator_bulk_disable(adv->num_supplies, adv->supplies);
1029*4882a593Smuzhiyun }
1030*4882a593Smuzhiyun
adv7511_cec_register_volatile(struct device * dev,unsigned int reg)1031*4882a593Smuzhiyun static bool adv7511_cec_register_volatile(struct device *dev, unsigned int reg)
1032*4882a593Smuzhiyun {
1033*4882a593Smuzhiyun struct i2c_client *i2c = to_i2c_client(dev);
1034*4882a593Smuzhiyun struct adv7511 *adv7511 = i2c_get_clientdata(i2c);
1035*4882a593Smuzhiyun
1036*4882a593Smuzhiyun if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
1037*4882a593Smuzhiyun reg -= ADV7533_REG_CEC_OFFSET;
1038*4882a593Smuzhiyun
1039*4882a593Smuzhiyun switch (reg) {
1040*4882a593Smuzhiyun case ADV7511_REG_CEC_RX_FRAME_HDR:
1041*4882a593Smuzhiyun case ADV7511_REG_CEC_RX_FRAME_DATA0...
1042*4882a593Smuzhiyun ADV7511_REG_CEC_RX_FRAME_DATA0 + 14:
1043*4882a593Smuzhiyun case ADV7511_REG_CEC_RX_FRAME_LEN:
1044*4882a593Smuzhiyun case ADV7511_REG_CEC_RX_BUFFERS:
1045*4882a593Smuzhiyun case ADV7511_REG_CEC_TX_LOW_DRV_CNT:
1046*4882a593Smuzhiyun return true;
1047*4882a593Smuzhiyun }
1048*4882a593Smuzhiyun
1049*4882a593Smuzhiyun return false;
1050*4882a593Smuzhiyun }
1051*4882a593Smuzhiyun
1052*4882a593Smuzhiyun static const struct regmap_config adv7511_cec_regmap_config = {
1053*4882a593Smuzhiyun .reg_bits = 8,
1054*4882a593Smuzhiyun .val_bits = 8,
1055*4882a593Smuzhiyun
1056*4882a593Smuzhiyun .max_register = 0xff,
1057*4882a593Smuzhiyun .cache_type = REGCACHE_RBTREE,
1058*4882a593Smuzhiyun .volatile_reg = adv7511_cec_register_volatile,
1059*4882a593Smuzhiyun };
1060*4882a593Smuzhiyun
adv7511_init_cec_regmap(struct adv7511 * adv)1061*4882a593Smuzhiyun static int adv7511_init_cec_regmap(struct adv7511 *adv)
1062*4882a593Smuzhiyun {
1063*4882a593Smuzhiyun int ret;
1064*4882a593Smuzhiyun
1065*4882a593Smuzhiyun adv->i2c_cec = i2c_new_ancillary_device(adv->i2c_main, "cec",
1066*4882a593Smuzhiyun ADV7511_CEC_I2C_ADDR_DEFAULT);
1067*4882a593Smuzhiyun if (IS_ERR(adv->i2c_cec))
1068*4882a593Smuzhiyun return PTR_ERR(adv->i2c_cec);
1069*4882a593Smuzhiyun
1070*4882a593Smuzhiyun regmap_write(adv->regmap, ADV7511_REG_CEC_I2C_ADDR,
1071*4882a593Smuzhiyun adv->i2c_cec->addr << 1);
1072*4882a593Smuzhiyun
1073*4882a593Smuzhiyun i2c_set_clientdata(adv->i2c_cec, adv);
1074*4882a593Smuzhiyun
1075*4882a593Smuzhiyun adv->regmap_cec = devm_regmap_init_i2c(adv->i2c_cec,
1076*4882a593Smuzhiyun &adv7511_cec_regmap_config);
1077*4882a593Smuzhiyun if (IS_ERR(adv->regmap_cec)) {
1078*4882a593Smuzhiyun ret = PTR_ERR(adv->regmap_cec);
1079*4882a593Smuzhiyun goto err;
1080*4882a593Smuzhiyun }
1081*4882a593Smuzhiyun
1082*4882a593Smuzhiyun if (adv->type == ADV7533 || adv->type == ADV7535) {
1083*4882a593Smuzhiyun ret = adv7533_patch_cec_registers(adv);
1084*4882a593Smuzhiyun if (ret)
1085*4882a593Smuzhiyun goto err;
1086*4882a593Smuzhiyun }
1087*4882a593Smuzhiyun
1088*4882a593Smuzhiyun return 0;
1089*4882a593Smuzhiyun err:
1090*4882a593Smuzhiyun i2c_unregister_device(adv->i2c_cec);
1091*4882a593Smuzhiyun return ret;
1092*4882a593Smuzhiyun }
1093*4882a593Smuzhiyun
adv7511_parse_dt(struct device_node * np,struct adv7511_link_config * config)1094*4882a593Smuzhiyun static int adv7511_parse_dt(struct device_node *np,
1095*4882a593Smuzhiyun struct adv7511_link_config *config)
1096*4882a593Smuzhiyun {
1097*4882a593Smuzhiyun const char *str;
1098*4882a593Smuzhiyun int ret;
1099*4882a593Smuzhiyun
1100*4882a593Smuzhiyun of_property_read_u32(np, "adi,input-depth", &config->input_color_depth);
1101*4882a593Smuzhiyun if (config->input_color_depth != 8 && config->input_color_depth != 10 &&
1102*4882a593Smuzhiyun config->input_color_depth != 12)
1103*4882a593Smuzhiyun return -EINVAL;
1104*4882a593Smuzhiyun
1105*4882a593Smuzhiyun ret = of_property_read_string(np, "adi,input-colorspace", &str);
1106*4882a593Smuzhiyun if (ret < 0)
1107*4882a593Smuzhiyun return ret;
1108*4882a593Smuzhiyun
1109*4882a593Smuzhiyun if (!strcmp(str, "rgb"))
1110*4882a593Smuzhiyun config->input_colorspace = HDMI_COLORSPACE_RGB;
1111*4882a593Smuzhiyun else if (!strcmp(str, "yuv422"))
1112*4882a593Smuzhiyun config->input_colorspace = HDMI_COLORSPACE_YUV422;
1113*4882a593Smuzhiyun else if (!strcmp(str, "yuv444"))
1114*4882a593Smuzhiyun config->input_colorspace = HDMI_COLORSPACE_YUV444;
1115*4882a593Smuzhiyun else
1116*4882a593Smuzhiyun return -EINVAL;
1117*4882a593Smuzhiyun
1118*4882a593Smuzhiyun ret = of_property_read_string(np, "adi,input-clock", &str);
1119*4882a593Smuzhiyun if (ret < 0)
1120*4882a593Smuzhiyun return ret;
1121*4882a593Smuzhiyun
1122*4882a593Smuzhiyun if (!strcmp(str, "1x"))
1123*4882a593Smuzhiyun config->input_clock = ADV7511_INPUT_CLOCK_1X;
1124*4882a593Smuzhiyun else if (!strcmp(str, "2x"))
1125*4882a593Smuzhiyun config->input_clock = ADV7511_INPUT_CLOCK_2X;
1126*4882a593Smuzhiyun else if (!strcmp(str, "ddr"))
1127*4882a593Smuzhiyun config->input_clock = ADV7511_INPUT_CLOCK_DDR;
1128*4882a593Smuzhiyun else
1129*4882a593Smuzhiyun return -EINVAL;
1130*4882a593Smuzhiyun
1131*4882a593Smuzhiyun if (config->input_colorspace == HDMI_COLORSPACE_YUV422 ||
1132*4882a593Smuzhiyun config->input_clock != ADV7511_INPUT_CLOCK_1X) {
1133*4882a593Smuzhiyun ret = of_property_read_u32(np, "adi,input-style",
1134*4882a593Smuzhiyun &config->input_style);
1135*4882a593Smuzhiyun if (ret)
1136*4882a593Smuzhiyun return ret;
1137*4882a593Smuzhiyun
1138*4882a593Smuzhiyun if (config->input_style < 1 || config->input_style > 3)
1139*4882a593Smuzhiyun return -EINVAL;
1140*4882a593Smuzhiyun
1141*4882a593Smuzhiyun ret = of_property_read_string(np, "adi,input-justification",
1142*4882a593Smuzhiyun &str);
1143*4882a593Smuzhiyun if (ret < 0)
1144*4882a593Smuzhiyun return ret;
1145*4882a593Smuzhiyun
1146*4882a593Smuzhiyun if (!strcmp(str, "left"))
1147*4882a593Smuzhiyun config->input_justification =
1148*4882a593Smuzhiyun ADV7511_INPUT_JUSTIFICATION_LEFT;
1149*4882a593Smuzhiyun else if (!strcmp(str, "evenly"))
1150*4882a593Smuzhiyun config->input_justification =
1151*4882a593Smuzhiyun ADV7511_INPUT_JUSTIFICATION_EVENLY;
1152*4882a593Smuzhiyun else if (!strcmp(str, "right"))
1153*4882a593Smuzhiyun config->input_justification =
1154*4882a593Smuzhiyun ADV7511_INPUT_JUSTIFICATION_RIGHT;
1155*4882a593Smuzhiyun else
1156*4882a593Smuzhiyun return -EINVAL;
1157*4882a593Smuzhiyun
1158*4882a593Smuzhiyun } else {
1159*4882a593Smuzhiyun config->input_style = 1;
1160*4882a593Smuzhiyun config->input_justification = ADV7511_INPUT_JUSTIFICATION_LEFT;
1161*4882a593Smuzhiyun }
1162*4882a593Smuzhiyun
1163*4882a593Smuzhiyun of_property_read_u32(np, "adi,clock-delay", &config->clock_delay);
1164*4882a593Smuzhiyun if (config->clock_delay < -1200 || config->clock_delay > 1600)
1165*4882a593Smuzhiyun return -EINVAL;
1166*4882a593Smuzhiyun
1167*4882a593Smuzhiyun config->embedded_sync = of_property_read_bool(np, "adi,embedded-sync");
1168*4882a593Smuzhiyun
1169*4882a593Smuzhiyun /* Hardcode the sync pulse configurations for now. */
1170*4882a593Smuzhiyun config->sync_pulse = ADV7511_INPUT_SYNC_PULSE_NONE;
1171*4882a593Smuzhiyun config->vsync_polarity = ADV7511_SYNC_POLARITY_PASSTHROUGH;
1172*4882a593Smuzhiyun config->hsync_polarity = ADV7511_SYNC_POLARITY_PASSTHROUGH;
1173*4882a593Smuzhiyun
1174*4882a593Smuzhiyun return 0;
1175*4882a593Smuzhiyun }
1176*4882a593Smuzhiyun
adv7511_probe(struct i2c_client * i2c,const struct i2c_device_id * id)1177*4882a593Smuzhiyun static int adv7511_probe(struct i2c_client *i2c, const struct i2c_device_id *id)
1178*4882a593Smuzhiyun {
1179*4882a593Smuzhiyun struct adv7511_link_config link_config;
1180*4882a593Smuzhiyun struct adv7511 *adv7511;
1181*4882a593Smuzhiyun struct device *dev = &i2c->dev;
1182*4882a593Smuzhiyun unsigned int val;
1183*4882a593Smuzhiyun int ret;
1184*4882a593Smuzhiyun
1185*4882a593Smuzhiyun if (!dev->of_node)
1186*4882a593Smuzhiyun return -EINVAL;
1187*4882a593Smuzhiyun
1188*4882a593Smuzhiyun adv7511 = devm_kzalloc(dev, sizeof(*adv7511), GFP_KERNEL);
1189*4882a593Smuzhiyun if (!adv7511)
1190*4882a593Smuzhiyun return -ENOMEM;
1191*4882a593Smuzhiyun
1192*4882a593Smuzhiyun adv7511->i2c_main = i2c;
1193*4882a593Smuzhiyun adv7511->powered = false;
1194*4882a593Smuzhiyun adv7511->status = connector_status_disconnected;
1195*4882a593Smuzhiyun
1196*4882a593Smuzhiyun if (dev->of_node)
1197*4882a593Smuzhiyun adv7511->type = (enum adv7511_type)of_device_get_match_data(dev);
1198*4882a593Smuzhiyun else
1199*4882a593Smuzhiyun adv7511->type = id->driver_data;
1200*4882a593Smuzhiyun
1201*4882a593Smuzhiyun memset(&link_config, 0, sizeof(link_config));
1202*4882a593Smuzhiyun
1203*4882a593Smuzhiyun if (adv7511->type == ADV7511)
1204*4882a593Smuzhiyun ret = adv7511_parse_dt(dev->of_node, &link_config);
1205*4882a593Smuzhiyun else
1206*4882a593Smuzhiyun ret = adv7533_parse_dt(dev->of_node, adv7511);
1207*4882a593Smuzhiyun if (ret)
1208*4882a593Smuzhiyun return ret;
1209*4882a593Smuzhiyun
1210*4882a593Smuzhiyun ret = adv7511_init_regulators(adv7511);
1211*4882a593Smuzhiyun if (ret) {
1212*4882a593Smuzhiyun dev_err(dev, "failed to init regulators\n");
1213*4882a593Smuzhiyun return ret;
1214*4882a593Smuzhiyun }
1215*4882a593Smuzhiyun
1216*4882a593Smuzhiyun /*
1217*4882a593Smuzhiyun * The power down GPIO is optional. If present, toggle it from active to
1218*4882a593Smuzhiyun * inactive to wake up the encoder.
1219*4882a593Smuzhiyun */
1220*4882a593Smuzhiyun adv7511->gpio_pd = devm_gpiod_get_optional(dev, "pd", GPIOD_OUT_HIGH);
1221*4882a593Smuzhiyun if (IS_ERR(adv7511->gpio_pd)) {
1222*4882a593Smuzhiyun ret = PTR_ERR(adv7511->gpio_pd);
1223*4882a593Smuzhiyun goto uninit_regulators;
1224*4882a593Smuzhiyun }
1225*4882a593Smuzhiyun
1226*4882a593Smuzhiyun if (adv7511->gpio_pd) {
1227*4882a593Smuzhiyun usleep_range(5000, 6000);
1228*4882a593Smuzhiyun gpiod_set_value_cansleep(adv7511->gpio_pd, 0);
1229*4882a593Smuzhiyun }
1230*4882a593Smuzhiyun
1231*4882a593Smuzhiyun adv7511->regmap = devm_regmap_init_i2c(i2c, &adv7511_regmap_config);
1232*4882a593Smuzhiyun if (IS_ERR(adv7511->regmap)) {
1233*4882a593Smuzhiyun ret = PTR_ERR(adv7511->regmap);
1234*4882a593Smuzhiyun goto uninit_regulators;
1235*4882a593Smuzhiyun }
1236*4882a593Smuzhiyun
1237*4882a593Smuzhiyun ret = regmap_read(adv7511->regmap, ADV7511_REG_CHIP_REVISION, &val);
1238*4882a593Smuzhiyun if (ret)
1239*4882a593Smuzhiyun goto uninit_regulators;
1240*4882a593Smuzhiyun dev_dbg(dev, "Rev. %d\n", val);
1241*4882a593Smuzhiyun
1242*4882a593Smuzhiyun if (adv7511->type == ADV7511)
1243*4882a593Smuzhiyun ret = regmap_register_patch(adv7511->regmap,
1244*4882a593Smuzhiyun adv7511_fixed_registers,
1245*4882a593Smuzhiyun ARRAY_SIZE(adv7511_fixed_registers));
1246*4882a593Smuzhiyun else
1247*4882a593Smuzhiyun ret = adv7533_patch_registers(adv7511);
1248*4882a593Smuzhiyun if (ret)
1249*4882a593Smuzhiyun goto uninit_regulators;
1250*4882a593Smuzhiyun
1251*4882a593Smuzhiyun adv7511_packet_disable(adv7511, 0xffff);
1252*4882a593Smuzhiyun
1253*4882a593Smuzhiyun adv7511->i2c_edid = i2c_new_ancillary_device(i2c, "edid",
1254*4882a593Smuzhiyun ADV7511_EDID_I2C_ADDR_DEFAULT);
1255*4882a593Smuzhiyun if (IS_ERR(adv7511->i2c_edid)) {
1256*4882a593Smuzhiyun ret = PTR_ERR(adv7511->i2c_edid);
1257*4882a593Smuzhiyun goto uninit_regulators;
1258*4882a593Smuzhiyun }
1259*4882a593Smuzhiyun
1260*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_EDID_I2C_ADDR,
1261*4882a593Smuzhiyun adv7511->i2c_edid->addr << 1);
1262*4882a593Smuzhiyun
1263*4882a593Smuzhiyun adv7511->i2c_packet = i2c_new_ancillary_device(i2c, "packet",
1264*4882a593Smuzhiyun ADV7511_PACKET_I2C_ADDR_DEFAULT);
1265*4882a593Smuzhiyun if (IS_ERR(adv7511->i2c_packet)) {
1266*4882a593Smuzhiyun ret = PTR_ERR(adv7511->i2c_packet);
1267*4882a593Smuzhiyun goto err_i2c_unregister_edid;
1268*4882a593Smuzhiyun }
1269*4882a593Smuzhiyun
1270*4882a593Smuzhiyun regmap_write(adv7511->regmap, ADV7511_REG_PACKET_I2C_ADDR,
1271*4882a593Smuzhiyun adv7511->i2c_packet->addr << 1);
1272*4882a593Smuzhiyun
1273*4882a593Smuzhiyun ret = adv7511_init_cec_regmap(adv7511);
1274*4882a593Smuzhiyun if (ret)
1275*4882a593Smuzhiyun goto err_i2c_unregister_packet;
1276*4882a593Smuzhiyun
1277*4882a593Smuzhiyun INIT_WORK(&adv7511->hpd_work, adv7511_hpd_work);
1278*4882a593Smuzhiyun
1279*4882a593Smuzhiyun if (i2c->irq) {
1280*4882a593Smuzhiyun init_waitqueue_head(&adv7511->wq);
1281*4882a593Smuzhiyun
1282*4882a593Smuzhiyun ret = devm_request_threaded_irq(dev, i2c->irq, NULL,
1283*4882a593Smuzhiyun adv7511_irq_handler,
1284*4882a593Smuzhiyun IRQF_ONESHOT, dev_name(dev),
1285*4882a593Smuzhiyun adv7511);
1286*4882a593Smuzhiyun if (ret)
1287*4882a593Smuzhiyun goto err_unregister_cec;
1288*4882a593Smuzhiyun }
1289*4882a593Smuzhiyun
1290*4882a593Smuzhiyun adv7511_power_off(adv7511);
1291*4882a593Smuzhiyun
1292*4882a593Smuzhiyun i2c_set_clientdata(i2c, adv7511);
1293*4882a593Smuzhiyun
1294*4882a593Smuzhiyun if (adv7511->type == ADV7511)
1295*4882a593Smuzhiyun adv7511_set_link_config(adv7511, &link_config);
1296*4882a593Smuzhiyun
1297*4882a593Smuzhiyun ret = adv7511_cec_init(dev, adv7511);
1298*4882a593Smuzhiyun if (ret)
1299*4882a593Smuzhiyun goto err_unregister_cec;
1300*4882a593Smuzhiyun
1301*4882a593Smuzhiyun adv7511->bridge.funcs = &adv7511_bridge_funcs;
1302*4882a593Smuzhiyun adv7511->bridge.ops = DRM_BRIDGE_OP_DETECT | DRM_BRIDGE_OP_EDID
1303*4882a593Smuzhiyun | DRM_BRIDGE_OP_HPD;
1304*4882a593Smuzhiyun adv7511->bridge.of_node = dev->of_node;
1305*4882a593Smuzhiyun adv7511->bridge.type = DRM_MODE_CONNECTOR_HDMIA;
1306*4882a593Smuzhiyun
1307*4882a593Smuzhiyun drm_bridge_add(&adv7511->bridge);
1308*4882a593Smuzhiyun
1309*4882a593Smuzhiyun adv7511_audio_init(dev, adv7511);
1310*4882a593Smuzhiyun return 0;
1311*4882a593Smuzhiyun
1312*4882a593Smuzhiyun err_unregister_cec:
1313*4882a593Smuzhiyun cec_unregister_adapter(adv7511->cec_adap);
1314*4882a593Smuzhiyun i2c_unregister_device(adv7511->i2c_cec);
1315*4882a593Smuzhiyun if (adv7511->cec_clk)
1316*4882a593Smuzhiyun clk_disable_unprepare(adv7511->cec_clk);
1317*4882a593Smuzhiyun err_i2c_unregister_packet:
1318*4882a593Smuzhiyun i2c_unregister_device(adv7511->i2c_packet);
1319*4882a593Smuzhiyun err_i2c_unregister_edid:
1320*4882a593Smuzhiyun i2c_unregister_device(adv7511->i2c_edid);
1321*4882a593Smuzhiyun uninit_regulators:
1322*4882a593Smuzhiyun adv7511_uninit_regulators(adv7511);
1323*4882a593Smuzhiyun
1324*4882a593Smuzhiyun return ret;
1325*4882a593Smuzhiyun }
1326*4882a593Smuzhiyun
adv7511_remove(struct i2c_client * i2c)1327*4882a593Smuzhiyun static int adv7511_remove(struct i2c_client *i2c)
1328*4882a593Smuzhiyun {
1329*4882a593Smuzhiyun struct adv7511 *adv7511 = i2c_get_clientdata(i2c);
1330*4882a593Smuzhiyun
1331*4882a593Smuzhiyun if (adv7511->type == ADV7533 || adv7511->type == ADV7535)
1332*4882a593Smuzhiyun adv7533_detach_dsi(adv7511);
1333*4882a593Smuzhiyun i2c_unregister_device(adv7511->i2c_cec);
1334*4882a593Smuzhiyun if (adv7511->cec_clk)
1335*4882a593Smuzhiyun clk_disable_unprepare(adv7511->cec_clk);
1336*4882a593Smuzhiyun
1337*4882a593Smuzhiyun adv7511_uninit_regulators(adv7511);
1338*4882a593Smuzhiyun
1339*4882a593Smuzhiyun drm_bridge_remove(&adv7511->bridge);
1340*4882a593Smuzhiyun
1341*4882a593Smuzhiyun adv7511_audio_exit(adv7511);
1342*4882a593Smuzhiyun
1343*4882a593Smuzhiyun cec_unregister_adapter(adv7511->cec_adap);
1344*4882a593Smuzhiyun
1345*4882a593Smuzhiyun i2c_unregister_device(adv7511->i2c_packet);
1346*4882a593Smuzhiyun i2c_unregister_device(adv7511->i2c_edid);
1347*4882a593Smuzhiyun
1348*4882a593Smuzhiyun return 0;
1349*4882a593Smuzhiyun }
1350*4882a593Smuzhiyun
1351*4882a593Smuzhiyun static const struct i2c_device_id adv7511_i2c_ids[] = {
1352*4882a593Smuzhiyun { "adv7511", ADV7511 },
1353*4882a593Smuzhiyun { "adv7511w", ADV7511 },
1354*4882a593Smuzhiyun { "adv7513", ADV7511 },
1355*4882a593Smuzhiyun { "adv7533", ADV7533 },
1356*4882a593Smuzhiyun { "adv7535", ADV7535 },
1357*4882a593Smuzhiyun { }
1358*4882a593Smuzhiyun };
1359*4882a593Smuzhiyun MODULE_DEVICE_TABLE(i2c, adv7511_i2c_ids);
1360*4882a593Smuzhiyun
1361*4882a593Smuzhiyun static const struct of_device_id adv7511_of_ids[] = {
1362*4882a593Smuzhiyun { .compatible = "adi,adv7511", .data = (void *)ADV7511 },
1363*4882a593Smuzhiyun { .compatible = "adi,adv7511w", .data = (void *)ADV7511 },
1364*4882a593Smuzhiyun { .compatible = "adi,adv7513", .data = (void *)ADV7511 },
1365*4882a593Smuzhiyun { .compatible = "adi,adv7533", .data = (void *)ADV7533 },
1366*4882a593Smuzhiyun { .compatible = "adi,adv7535", .data = (void *)ADV7535 },
1367*4882a593Smuzhiyun { }
1368*4882a593Smuzhiyun };
1369*4882a593Smuzhiyun MODULE_DEVICE_TABLE(of, adv7511_of_ids);
1370*4882a593Smuzhiyun
1371*4882a593Smuzhiyun static struct mipi_dsi_driver adv7533_dsi_driver = {
1372*4882a593Smuzhiyun .driver.name = "adv7533",
1373*4882a593Smuzhiyun };
1374*4882a593Smuzhiyun
1375*4882a593Smuzhiyun static struct i2c_driver adv7511_driver = {
1376*4882a593Smuzhiyun .driver = {
1377*4882a593Smuzhiyun .name = "adv7511",
1378*4882a593Smuzhiyun .of_match_table = adv7511_of_ids,
1379*4882a593Smuzhiyun },
1380*4882a593Smuzhiyun .id_table = adv7511_i2c_ids,
1381*4882a593Smuzhiyun .probe = adv7511_probe,
1382*4882a593Smuzhiyun .remove = adv7511_remove,
1383*4882a593Smuzhiyun };
1384*4882a593Smuzhiyun
adv7511_init(void)1385*4882a593Smuzhiyun static int __init adv7511_init(void)
1386*4882a593Smuzhiyun {
1387*4882a593Smuzhiyun int ret;
1388*4882a593Smuzhiyun
1389*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_DRM_MIPI_DSI)) {
1390*4882a593Smuzhiyun ret = mipi_dsi_driver_register(&adv7533_dsi_driver);
1391*4882a593Smuzhiyun if (ret)
1392*4882a593Smuzhiyun return ret;
1393*4882a593Smuzhiyun }
1394*4882a593Smuzhiyun
1395*4882a593Smuzhiyun ret = i2c_add_driver(&adv7511_driver);
1396*4882a593Smuzhiyun if (ret) {
1397*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1398*4882a593Smuzhiyun mipi_dsi_driver_unregister(&adv7533_dsi_driver);
1399*4882a593Smuzhiyun }
1400*4882a593Smuzhiyun
1401*4882a593Smuzhiyun return ret;
1402*4882a593Smuzhiyun }
1403*4882a593Smuzhiyun module_init(adv7511_init);
1404*4882a593Smuzhiyun
adv7511_exit(void)1405*4882a593Smuzhiyun static void __exit adv7511_exit(void)
1406*4882a593Smuzhiyun {
1407*4882a593Smuzhiyun i2c_del_driver(&adv7511_driver);
1408*4882a593Smuzhiyun
1409*4882a593Smuzhiyun if (IS_ENABLED(CONFIG_DRM_MIPI_DSI))
1410*4882a593Smuzhiyun mipi_dsi_driver_unregister(&adv7533_dsi_driver);
1411*4882a593Smuzhiyun }
1412*4882a593Smuzhiyun module_exit(adv7511_exit);
1413*4882a593Smuzhiyun
1414*4882a593Smuzhiyun MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
1415*4882a593Smuzhiyun MODULE_DESCRIPTION("ADV7511 HDMI transmitter driver");
1416*4882a593Smuzhiyun MODULE_LICENSE("GPL");
1417