1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0+
2*4882a593Smuzhiyun // Copyright 2018 IBM Corporation
3*4882a593Smuzhiyun
4*4882a593Smuzhiyun #include <linux/clk.h>
5*4882a593Smuzhiyun #include <linux/dma-mapping.h>
6*4882a593Smuzhiyun #include <linux/irq.h>
7*4882a593Smuzhiyun #include <linux/mfd/syscon.h>
8*4882a593Smuzhiyun #include <linux/module.h>
9*4882a593Smuzhiyun #include <linux/of.h>
10*4882a593Smuzhiyun #include <linux/of_reserved_mem.h>
11*4882a593Smuzhiyun #include <linux/platform_device.h>
12*4882a593Smuzhiyun #include <linux/regmap.h>
13*4882a593Smuzhiyun #include <linux/reset.h>
14*4882a593Smuzhiyun
15*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
16*4882a593Smuzhiyun #include <drm/drm_crtc_helper.h>
17*4882a593Smuzhiyun #include <drm/drm_device.h>
18*4882a593Smuzhiyun #include <drm/drm_fb_cma_helper.h>
19*4882a593Smuzhiyun #include <drm/drm_fb_helper.h>
20*4882a593Smuzhiyun #include <drm/drm_gem_cma_helper.h>
21*4882a593Smuzhiyun #include <drm/drm_gem_framebuffer_helper.h>
22*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
23*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h>
24*4882a593Smuzhiyun #include <drm/drm_vblank.h>
25*4882a593Smuzhiyun #include <drm/drm_drv.h>
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include "aspeed_gfx.h"
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun /**
30*4882a593Smuzhiyun * DOC: ASPEED GFX Driver
31*4882a593Smuzhiyun *
32*4882a593Smuzhiyun * This driver is for the ASPEED BMC SoC's 'GFX' display hardware, also called
33*4882a593Smuzhiyun * the 'SOC Display Controller' in the datasheet. This driver runs on the ARM
34*4882a593Smuzhiyun * based BMC systems, unlike the ast driver which runs on a host CPU and is for
35*4882a593Smuzhiyun * a PCIe graphics device.
36*4882a593Smuzhiyun *
37*4882a593Smuzhiyun * The AST2500 supports a total of 3 output paths:
38*4882a593Smuzhiyun *
39*4882a593Smuzhiyun * 1. VGA output, the output target can choose either or both to the DAC
40*4882a593Smuzhiyun * or DVO interface.
41*4882a593Smuzhiyun *
42*4882a593Smuzhiyun * 2. Graphics CRT output, the output target can choose either or both to
43*4882a593Smuzhiyun * the DAC or DVO interface.
44*4882a593Smuzhiyun *
45*4882a593Smuzhiyun * 3. Video input from DVO, the video input can be used for video engine
46*4882a593Smuzhiyun * capture or DAC display output.
47*4882a593Smuzhiyun *
48*4882a593Smuzhiyun * Output options are selected in SCU2C.
49*4882a593Smuzhiyun *
50*4882a593Smuzhiyun * The "VGA mode" device is the PCI attached controller. The "Graphics CRT"
51*4882a593Smuzhiyun * is the ARM's internal display controller.
52*4882a593Smuzhiyun *
53*4882a593Smuzhiyun * The driver only supports a simple configuration consisting of a 40MHz
54*4882a593Smuzhiyun * pixel clock, fixed by hardware limitations, and the VGA output path.
55*4882a593Smuzhiyun *
56*4882a593Smuzhiyun * The driver was written with the 'AST2500 Software Programming Guide' v17,
57*4882a593Smuzhiyun * which is available under NDA from ASPEED.
58*4882a593Smuzhiyun */
59*4882a593Smuzhiyun
60*4882a593Smuzhiyun static const struct drm_mode_config_funcs aspeed_gfx_mode_config_funcs = {
61*4882a593Smuzhiyun .fb_create = drm_gem_fb_create,
62*4882a593Smuzhiyun .atomic_check = drm_atomic_helper_check,
63*4882a593Smuzhiyun .atomic_commit = drm_atomic_helper_commit,
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun
aspeed_gfx_setup_mode_config(struct drm_device * drm)66*4882a593Smuzhiyun static int aspeed_gfx_setup_mode_config(struct drm_device *drm)
67*4882a593Smuzhiyun {
68*4882a593Smuzhiyun int ret;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun ret = drmm_mode_config_init(drm);
71*4882a593Smuzhiyun if (ret)
72*4882a593Smuzhiyun return ret;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun drm->mode_config.min_width = 0;
75*4882a593Smuzhiyun drm->mode_config.min_height = 0;
76*4882a593Smuzhiyun drm->mode_config.max_width = 800;
77*4882a593Smuzhiyun drm->mode_config.max_height = 600;
78*4882a593Smuzhiyun drm->mode_config.funcs = &aspeed_gfx_mode_config_funcs;
79*4882a593Smuzhiyun
80*4882a593Smuzhiyun return ret;
81*4882a593Smuzhiyun }
82*4882a593Smuzhiyun
aspeed_gfx_irq_handler(int irq,void * data)83*4882a593Smuzhiyun static irqreturn_t aspeed_gfx_irq_handler(int irq, void *data)
84*4882a593Smuzhiyun {
85*4882a593Smuzhiyun struct drm_device *drm = data;
86*4882a593Smuzhiyun struct aspeed_gfx *priv = to_aspeed_gfx(drm);
87*4882a593Smuzhiyun u32 reg;
88*4882a593Smuzhiyun
89*4882a593Smuzhiyun reg = readl(priv->base + CRT_CTRL1);
90*4882a593Smuzhiyun
91*4882a593Smuzhiyun if (reg & CRT_CTRL_VERTICAL_INTR_STS) {
92*4882a593Smuzhiyun drm_crtc_handle_vblank(&priv->pipe.crtc);
93*4882a593Smuzhiyun writel(reg, priv->base + CRT_CTRL1);
94*4882a593Smuzhiyun return IRQ_HANDLED;
95*4882a593Smuzhiyun }
96*4882a593Smuzhiyun
97*4882a593Smuzhiyun return IRQ_NONE;
98*4882a593Smuzhiyun }
99*4882a593Smuzhiyun
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun
aspeed_gfx_load(struct drm_device * drm)102*4882a593Smuzhiyun static int aspeed_gfx_load(struct drm_device *drm)
103*4882a593Smuzhiyun {
104*4882a593Smuzhiyun struct platform_device *pdev = to_platform_device(drm->dev);
105*4882a593Smuzhiyun struct aspeed_gfx *priv = to_aspeed_gfx(drm);
106*4882a593Smuzhiyun struct resource *res;
107*4882a593Smuzhiyun int ret;
108*4882a593Smuzhiyun
109*4882a593Smuzhiyun res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
110*4882a593Smuzhiyun priv->base = devm_ioremap_resource(drm->dev, res);
111*4882a593Smuzhiyun if (IS_ERR(priv->base))
112*4882a593Smuzhiyun return PTR_ERR(priv->base);
113*4882a593Smuzhiyun
114*4882a593Smuzhiyun priv->scu = syscon_regmap_lookup_by_compatible("aspeed,ast2500-scu");
115*4882a593Smuzhiyun if (IS_ERR(priv->scu)) {
116*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to find SCU regmap\n");
117*4882a593Smuzhiyun return PTR_ERR(priv->scu);
118*4882a593Smuzhiyun }
119*4882a593Smuzhiyun
120*4882a593Smuzhiyun ret = of_reserved_mem_device_init(drm->dev);
121*4882a593Smuzhiyun if (ret) {
122*4882a593Smuzhiyun dev_err(&pdev->dev,
123*4882a593Smuzhiyun "failed to initialize reserved mem: %d\n", ret);
124*4882a593Smuzhiyun return ret;
125*4882a593Smuzhiyun }
126*4882a593Smuzhiyun
127*4882a593Smuzhiyun ret = dma_set_mask_and_coherent(drm->dev, DMA_BIT_MASK(32));
128*4882a593Smuzhiyun if (ret) {
129*4882a593Smuzhiyun dev_err(&pdev->dev, "failed to set DMA mask: %d\n", ret);
130*4882a593Smuzhiyun return ret;
131*4882a593Smuzhiyun }
132*4882a593Smuzhiyun
133*4882a593Smuzhiyun priv->rst = devm_reset_control_get_exclusive(&pdev->dev, NULL);
134*4882a593Smuzhiyun if (IS_ERR(priv->rst)) {
135*4882a593Smuzhiyun dev_err(&pdev->dev,
136*4882a593Smuzhiyun "missing or invalid reset controller device tree entry");
137*4882a593Smuzhiyun return PTR_ERR(priv->rst);
138*4882a593Smuzhiyun }
139*4882a593Smuzhiyun reset_control_deassert(priv->rst);
140*4882a593Smuzhiyun
141*4882a593Smuzhiyun priv->clk = devm_clk_get(drm->dev, NULL);
142*4882a593Smuzhiyun if (IS_ERR(priv->clk)) {
143*4882a593Smuzhiyun dev_err(&pdev->dev,
144*4882a593Smuzhiyun "missing or invalid clk device tree entry");
145*4882a593Smuzhiyun return PTR_ERR(priv->clk);
146*4882a593Smuzhiyun }
147*4882a593Smuzhiyun clk_prepare_enable(priv->clk);
148*4882a593Smuzhiyun
149*4882a593Smuzhiyun /* Sanitize control registers */
150*4882a593Smuzhiyun writel(0, priv->base + CRT_CTRL1);
151*4882a593Smuzhiyun writel(0, priv->base + CRT_CTRL2);
152*4882a593Smuzhiyun
153*4882a593Smuzhiyun ret = aspeed_gfx_setup_mode_config(drm);
154*4882a593Smuzhiyun if (ret < 0)
155*4882a593Smuzhiyun return ret;
156*4882a593Smuzhiyun
157*4882a593Smuzhiyun ret = drm_vblank_init(drm, 1);
158*4882a593Smuzhiyun if (ret < 0) {
159*4882a593Smuzhiyun dev_err(drm->dev, "Failed to initialise vblank\n");
160*4882a593Smuzhiyun return ret;
161*4882a593Smuzhiyun }
162*4882a593Smuzhiyun
163*4882a593Smuzhiyun ret = aspeed_gfx_create_output(drm);
164*4882a593Smuzhiyun if (ret < 0) {
165*4882a593Smuzhiyun dev_err(drm->dev, "Failed to create outputs\n");
166*4882a593Smuzhiyun return ret;
167*4882a593Smuzhiyun }
168*4882a593Smuzhiyun
169*4882a593Smuzhiyun ret = aspeed_gfx_create_pipe(drm);
170*4882a593Smuzhiyun if (ret < 0) {
171*4882a593Smuzhiyun dev_err(drm->dev, "Cannot setup simple display pipe\n");
172*4882a593Smuzhiyun return ret;
173*4882a593Smuzhiyun }
174*4882a593Smuzhiyun
175*4882a593Smuzhiyun ret = devm_request_irq(drm->dev, platform_get_irq(pdev, 0),
176*4882a593Smuzhiyun aspeed_gfx_irq_handler, 0, "aspeed gfx", drm);
177*4882a593Smuzhiyun if (ret < 0) {
178*4882a593Smuzhiyun dev_err(drm->dev, "Failed to install IRQ handler\n");
179*4882a593Smuzhiyun return ret;
180*4882a593Smuzhiyun }
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun drm_mode_config_reset(drm);
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun return 0;
185*4882a593Smuzhiyun }
186*4882a593Smuzhiyun
aspeed_gfx_unload(struct drm_device * drm)187*4882a593Smuzhiyun static void aspeed_gfx_unload(struct drm_device *drm)
188*4882a593Smuzhiyun {
189*4882a593Smuzhiyun drm_kms_helper_poll_fini(drm);
190*4882a593Smuzhiyun }
191*4882a593Smuzhiyun
192*4882a593Smuzhiyun DEFINE_DRM_GEM_CMA_FOPS(fops);
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun static struct drm_driver aspeed_gfx_driver = {
195*4882a593Smuzhiyun .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
196*4882a593Smuzhiyun .gem_create_object = drm_gem_cma_create_object_default_funcs,
197*4882a593Smuzhiyun .dumb_create = drm_gem_cma_dumb_create,
198*4882a593Smuzhiyun .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
199*4882a593Smuzhiyun .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
200*4882a593Smuzhiyun .gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
201*4882a593Smuzhiyun .gem_prime_mmap = drm_gem_prime_mmap,
202*4882a593Smuzhiyun .fops = &fops,
203*4882a593Smuzhiyun .name = "aspeed-gfx-drm",
204*4882a593Smuzhiyun .desc = "ASPEED GFX DRM",
205*4882a593Smuzhiyun .date = "20180319",
206*4882a593Smuzhiyun .major = 1,
207*4882a593Smuzhiyun .minor = 0,
208*4882a593Smuzhiyun };
209*4882a593Smuzhiyun
210*4882a593Smuzhiyun static const struct of_device_id aspeed_gfx_match[] = {
211*4882a593Smuzhiyun { .compatible = "aspeed,ast2500-gfx" },
212*4882a593Smuzhiyun { }
213*4882a593Smuzhiyun };
214*4882a593Smuzhiyun
aspeed_gfx_probe(struct platform_device * pdev)215*4882a593Smuzhiyun static int aspeed_gfx_probe(struct platform_device *pdev)
216*4882a593Smuzhiyun {
217*4882a593Smuzhiyun struct aspeed_gfx *priv;
218*4882a593Smuzhiyun int ret;
219*4882a593Smuzhiyun
220*4882a593Smuzhiyun priv = devm_drm_dev_alloc(&pdev->dev, &aspeed_gfx_driver,
221*4882a593Smuzhiyun struct aspeed_gfx, drm);
222*4882a593Smuzhiyun if (IS_ERR(priv))
223*4882a593Smuzhiyun return PTR_ERR(priv);
224*4882a593Smuzhiyun
225*4882a593Smuzhiyun ret = aspeed_gfx_load(&priv->drm);
226*4882a593Smuzhiyun if (ret)
227*4882a593Smuzhiyun return ret;
228*4882a593Smuzhiyun
229*4882a593Smuzhiyun ret = drm_dev_register(&priv->drm, 0);
230*4882a593Smuzhiyun if (ret)
231*4882a593Smuzhiyun goto err_unload;
232*4882a593Smuzhiyun
233*4882a593Smuzhiyun drm_fbdev_generic_setup(&priv->drm, 32);
234*4882a593Smuzhiyun return 0;
235*4882a593Smuzhiyun
236*4882a593Smuzhiyun err_unload:
237*4882a593Smuzhiyun aspeed_gfx_unload(&priv->drm);
238*4882a593Smuzhiyun
239*4882a593Smuzhiyun return ret;
240*4882a593Smuzhiyun }
241*4882a593Smuzhiyun
aspeed_gfx_remove(struct platform_device * pdev)242*4882a593Smuzhiyun static int aspeed_gfx_remove(struct platform_device *pdev)
243*4882a593Smuzhiyun {
244*4882a593Smuzhiyun struct drm_device *drm = platform_get_drvdata(pdev);
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun drm_dev_unregister(drm);
247*4882a593Smuzhiyun aspeed_gfx_unload(drm);
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun return 0;
250*4882a593Smuzhiyun }
251*4882a593Smuzhiyun
252*4882a593Smuzhiyun static struct platform_driver aspeed_gfx_platform_driver = {
253*4882a593Smuzhiyun .probe = aspeed_gfx_probe,
254*4882a593Smuzhiyun .remove = aspeed_gfx_remove,
255*4882a593Smuzhiyun .driver = {
256*4882a593Smuzhiyun .name = "aspeed_gfx",
257*4882a593Smuzhiyun .of_match_table = aspeed_gfx_match,
258*4882a593Smuzhiyun },
259*4882a593Smuzhiyun };
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun module_platform_driver(aspeed_gfx_platform_driver);
262*4882a593Smuzhiyun
263*4882a593Smuzhiyun MODULE_AUTHOR("Joel Stanley <joel@jms.id.au>");
264*4882a593Smuzhiyun MODULE_DESCRIPTION("ASPEED BMC DRM/KMS driver");
265*4882a593Smuzhiyun MODULE_LICENSE("GPL");
266