1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0+ */ 2*4882a593Smuzhiyun /* Copyright 2018 IBM Corporation */ 3*4882a593Smuzhiyun 4*4882a593Smuzhiyun #include <drm/drm_device.h> 5*4882a593Smuzhiyun #include <drm/drm_simple_kms_helper.h> 6*4882a593Smuzhiyun 7*4882a593Smuzhiyun struct aspeed_gfx { 8*4882a593Smuzhiyun struct drm_device drm; 9*4882a593Smuzhiyun void __iomem *base; 10*4882a593Smuzhiyun struct clk *clk; 11*4882a593Smuzhiyun struct reset_control *rst; 12*4882a593Smuzhiyun struct regmap *scu; 13*4882a593Smuzhiyun 14*4882a593Smuzhiyun struct drm_simple_display_pipe pipe; 15*4882a593Smuzhiyun struct drm_connector connector; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun #define to_aspeed_gfx(x) container_of(x, struct aspeed_gfx, drm) 18*4882a593Smuzhiyun 19*4882a593Smuzhiyun int aspeed_gfx_create_pipe(struct drm_device *drm); 20*4882a593Smuzhiyun int aspeed_gfx_create_output(struct drm_device *drm); 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define CRT_CTRL1 0x60 /* CRT Control I */ 23*4882a593Smuzhiyun #define CRT_CTRL2 0x64 /* CRT Control II */ 24*4882a593Smuzhiyun #define CRT_STATUS 0x68 /* CRT Status */ 25*4882a593Smuzhiyun #define CRT_MISC 0x6c /* CRT Misc Setting */ 26*4882a593Smuzhiyun #define CRT_HORIZ0 0x70 /* CRT Horizontal Total & Display Enable End */ 27*4882a593Smuzhiyun #define CRT_HORIZ1 0x74 /* CRT Horizontal Retrace Start & End */ 28*4882a593Smuzhiyun #define CRT_VERT0 0x78 /* CRT Vertical Total & Display Enable End */ 29*4882a593Smuzhiyun #define CRT_VERT1 0x7C /* CRT Vertical Retrace Start & End */ 30*4882a593Smuzhiyun #define CRT_ADDR 0x80 /* CRT Display Starting Address */ 31*4882a593Smuzhiyun #define CRT_OFFSET 0x84 /* CRT Display Offset & Terminal Count */ 32*4882a593Smuzhiyun #define CRT_THROD 0x88 /* CRT Threshold */ 33*4882a593Smuzhiyun #define CRT_XSCALE 0x8C /* CRT Scaling-Up Factor */ 34*4882a593Smuzhiyun #define CRT_CURSOR0 0x90 /* CRT Hardware Cursor X & Y Offset */ 35*4882a593Smuzhiyun #define CRT_CURSOR1 0x94 /* CRT Hardware Cursor X & Y Position */ 36*4882a593Smuzhiyun #define CRT_CURSOR2 0x98 /* CRT Hardware Cursor Pattern Address */ 37*4882a593Smuzhiyun #define CRT_9C 0x9C 38*4882a593Smuzhiyun #define CRT_OSD_H 0xA0 /* CRT OSD Horizontal Start/End */ 39*4882a593Smuzhiyun #define CRT_OSD_V 0xA4 /* CRT OSD Vertical Start/End */ 40*4882a593Smuzhiyun #define CRT_OSD_ADDR 0xA8 /* CRT OSD Pattern Address */ 41*4882a593Smuzhiyun #define CRT_OSD_DISP 0xAC /* CRT OSD Offset */ 42*4882a593Smuzhiyun #define CRT_OSD_THRESH 0xB0 /* CRT OSD Threshold & Alpha */ 43*4882a593Smuzhiyun #define CRT_B4 0xB4 44*4882a593Smuzhiyun #define CRT_STS_V 0xB8 /* CRT Status V */ 45*4882a593Smuzhiyun #define CRT_SCRATCH 0xBC /* Scratchpad */ 46*4882a593Smuzhiyun #define CRT_BB0_ADDR 0xD0 /* CRT Display BB0 Starting Address */ 47*4882a593Smuzhiyun #define CRT_BB1_ADDR 0xD4 /* CRT Display BB1 Starting Address */ 48*4882a593Smuzhiyun #define CRT_BB_COUNT 0xD8 /* CRT Display BB Terminal Count */ 49*4882a593Smuzhiyun #define OSD_COLOR1 0xE0 /* OSD Color Palette Index 1 & 0 */ 50*4882a593Smuzhiyun #define OSD_COLOR2 0xE4 /* OSD Color Palette Index 3 & 2 */ 51*4882a593Smuzhiyun #define OSD_COLOR3 0xE8 /* OSD Color Palette Index 5 & 4 */ 52*4882a593Smuzhiyun #define OSD_COLOR4 0xEC /* OSD Color Palette Index 7 & 6 */ 53*4882a593Smuzhiyun #define OSD_COLOR5 0xF0 /* OSD Color Palette Index 9 & 8 */ 54*4882a593Smuzhiyun #define OSD_COLOR6 0xF4 /* OSD Color Palette Index 11 & 10 */ 55*4882a593Smuzhiyun #define OSD_COLOR7 0xF8 /* OSD Color Palette Index 13 & 12 */ 56*4882a593Smuzhiyun #define OSD_COLOR8 0xFC /* OSD Color Palette Index 15 & 14 */ 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* CTRL1 */ 59*4882a593Smuzhiyun #define CRT_CTRL_EN BIT(0) 60*4882a593Smuzhiyun #define CRT_CTRL_HW_CURSOR_EN BIT(1) 61*4882a593Smuzhiyun #define CRT_CTRL_OSD_EN BIT(2) 62*4882a593Smuzhiyun #define CRT_CTRL_INTERLACED BIT(3) 63*4882a593Smuzhiyun #define CRT_CTRL_COLOR_RGB565 (0 << 7) 64*4882a593Smuzhiyun #define CRT_CTRL_COLOR_YUV444 (1 << 7) 65*4882a593Smuzhiyun #define CRT_CTRL_COLOR_XRGB8888 (2 << 7) 66*4882a593Smuzhiyun #define CRT_CTRL_COLOR_RGB888 (3 << 7) 67*4882a593Smuzhiyun #define CRT_CTRL_COLOR_YUV444_2RGB (5 << 7) 68*4882a593Smuzhiyun #define CRT_CTRL_COLOR_YUV422 (7 << 7) 69*4882a593Smuzhiyun #define CRT_CTRL_COLOR_MASK GENMASK(9, 7) 70*4882a593Smuzhiyun #define CRT_CTRL_HSYNC_NEGATIVE BIT(16) 71*4882a593Smuzhiyun #define CRT_CTRL_VSYNC_NEGATIVE BIT(17) 72*4882a593Smuzhiyun #define CRT_CTRL_VERTICAL_INTR_EN BIT(30) 73*4882a593Smuzhiyun #define CRT_CTRL_VERTICAL_INTR_STS BIT(31) 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun /* CTRL2 */ 76*4882a593Smuzhiyun #define CRT_CTRL_DAC_EN BIT(0) 77*4882a593Smuzhiyun #define CRT_CTRL_VBLANK_LINE(x) (((x) << 20) & CRT_CTRL_VBLANK_LINE_MASK) 78*4882a593Smuzhiyun #define CRT_CTRL_VBLANK_LINE_MASK GENMASK(20, 31) 79*4882a593Smuzhiyun 80*4882a593Smuzhiyun /* CRT_HORIZ0 */ 81*4882a593Smuzhiyun #define CRT_H_TOTAL(x) (x) 82*4882a593Smuzhiyun #define CRT_H_DE(x) ((x) << 16) 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun /* CRT_HORIZ1 */ 85*4882a593Smuzhiyun #define CRT_H_RS_START(x) (x) 86*4882a593Smuzhiyun #define CRT_H_RS_END(x) ((x) << 16) 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun /* CRT_VIRT0 */ 89*4882a593Smuzhiyun #define CRT_V_TOTAL(x) (x) 90*4882a593Smuzhiyun #define CRT_V_DE(x) ((x) << 16) 91*4882a593Smuzhiyun 92*4882a593Smuzhiyun /* CRT_VIRT1 */ 93*4882a593Smuzhiyun #define CRT_V_RS_START(x) (x) 94*4882a593Smuzhiyun #define CRT_V_RS_END(x) ((x) << 16) 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* CRT_OFFSET */ 97*4882a593Smuzhiyun #define CRT_DISP_OFFSET(x) (x) 98*4882a593Smuzhiyun #define CRT_TERM_COUNT(x) ((x) << 16) 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun /* CRT_THROD */ 101*4882a593Smuzhiyun #define CRT_THROD_LOW(x) (x) 102*4882a593Smuzhiyun #define CRT_THROD_HIGH(x) ((x) << 8) 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun /* Default Threshold Seting */ 105*4882a593Smuzhiyun #define G5_CRT_THROD_VAL (CRT_THROD_LOW(0x24) | CRT_THROD_HIGH(0x3C)) 106