1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * Copyright (C) 2012 Russell King 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun #ifndef ARMADA_CRTC_H 6*4882a593Smuzhiyun #define ARMADA_CRTC_H 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #include <drm/drm_crtc.h> 9*4882a593Smuzhiyun 10*4882a593Smuzhiyun struct armada_gem_object; 11*4882a593Smuzhiyun 12*4882a593Smuzhiyun struct armada_regs { 13*4882a593Smuzhiyun uint32_t offset; 14*4882a593Smuzhiyun uint32_t mask; 15*4882a593Smuzhiyun uint32_t val; 16*4882a593Smuzhiyun }; 17*4882a593Smuzhiyun 18*4882a593Smuzhiyun #define armada_reg_queue_mod(_r, _i, _v, _m, _o) \ 19*4882a593Smuzhiyun do { \ 20*4882a593Smuzhiyun struct armada_regs *__reg = _r; \ 21*4882a593Smuzhiyun __reg[_i].offset = _o; \ 22*4882a593Smuzhiyun __reg[_i].mask = ~(_m); \ 23*4882a593Smuzhiyun __reg[_i].val = _v; \ 24*4882a593Smuzhiyun _i++; \ 25*4882a593Smuzhiyun } while (0) 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define armada_reg_queue_set(_r, _i, _v, _o) \ 28*4882a593Smuzhiyun armada_reg_queue_mod(_r, _i, _v, ~0, _o) 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define armada_reg_queue_end(_r, _i) \ 31*4882a593Smuzhiyun armada_reg_queue_mod(_r, _i, 0, 0, ~0) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct armada_crtc; 34*4882a593Smuzhiyun struct armada_variant; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct armada_crtc { 37*4882a593Smuzhiyun struct drm_crtc crtc; 38*4882a593Smuzhiyun const struct armada_variant *variant; 39*4882a593Smuzhiyun void *variant_data; 40*4882a593Smuzhiyun unsigned num; 41*4882a593Smuzhiyun void __iomem *base; 42*4882a593Smuzhiyun struct clk *clk; 43*4882a593Smuzhiyun struct { 44*4882a593Smuzhiyun uint32_t spu_v_h_total; 45*4882a593Smuzhiyun uint32_t spu_v_porch; 46*4882a593Smuzhiyun uint32_t spu_adv_reg; 47*4882a593Smuzhiyun } v[2]; 48*4882a593Smuzhiyun bool interlaced; 49*4882a593Smuzhiyun bool cursor_update; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun struct armada_gem_object *cursor_obj; 52*4882a593Smuzhiyun int cursor_x; 53*4882a593Smuzhiyun int cursor_y; 54*4882a593Smuzhiyun uint32_t cursor_hw_pos; 55*4882a593Smuzhiyun uint32_t cursor_hw_sz; 56*4882a593Smuzhiyun uint32_t cursor_w; 57*4882a593Smuzhiyun uint32_t cursor_h; 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun uint32_t cfg_dumb_ctrl; 60*4882a593Smuzhiyun uint32_t spu_iopad_ctrl; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun spinlock_t irq_lock; 63*4882a593Smuzhiyun uint32_t irq_ena; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun bool update_pending; 66*4882a593Smuzhiyun struct drm_pending_vblank_event *event; 67*4882a593Smuzhiyun struct armada_regs atomic_regs[32]; 68*4882a593Smuzhiyun struct armada_regs *regs; 69*4882a593Smuzhiyun unsigned int regs_idx; 70*4882a593Smuzhiyun }; 71*4882a593Smuzhiyun #define drm_to_armada_crtc(c) container_of(c, struct armada_crtc, crtc) 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun void armada_drm_crtc_update_regs(struct armada_crtc *, struct armada_regs *); 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun struct armada_clocking_params { 76*4882a593Smuzhiyun unsigned long permillage_min; 77*4882a593Smuzhiyun unsigned long permillage_max; 78*4882a593Smuzhiyun u32 settable; 79*4882a593Smuzhiyun u32 div_max; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun struct armada_clk_result { 83*4882a593Smuzhiyun unsigned long desired_clk_hz; 84*4882a593Smuzhiyun struct clk *clk; 85*4882a593Smuzhiyun u32 div; 86*4882a593Smuzhiyun }; 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun int armada_crtc_select_clock(struct armada_crtc *dcrtc, 89*4882a593Smuzhiyun struct armada_clk_result *res, 90*4882a593Smuzhiyun const struct armada_clocking_params *params, 91*4882a593Smuzhiyun struct clk *clks[], size_t num_clks, 92*4882a593Smuzhiyun unsigned long desired_khz); 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun extern struct platform_driver armada_lcd_platform_driver; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #endif 97