1*4882a593Smuzhiyun // SPDX-License-Identifier: GPL-2.0
2*4882a593Smuzhiyun /*
3*4882a593Smuzhiyun * (C) COPYRIGHT 2016 ARM Limited. All rights reserved.
4*4882a593Smuzhiyun * Author: Brian Starkey <brian.starkey@arm.com>
5*4882a593Smuzhiyun *
6*4882a593Smuzhiyun * ARM Mali DP Writeback connector implementation
7*4882a593Smuzhiyun */
8*4882a593Smuzhiyun
9*4882a593Smuzhiyun #include <drm/drm_atomic.h>
10*4882a593Smuzhiyun #include <drm/drm_atomic_helper.h>
11*4882a593Smuzhiyun #include <drm/drm_crtc.h>
12*4882a593Smuzhiyun #include <drm/drm_fb_cma_helper.h>
13*4882a593Smuzhiyun #include <drm/drm_fourcc.h>
14*4882a593Smuzhiyun #include <drm/drm_gem_cma_helper.h>
15*4882a593Smuzhiyun #include <drm/drm_probe_helper.h>
16*4882a593Smuzhiyun #include <drm/drm_writeback.h>
17*4882a593Smuzhiyun
18*4882a593Smuzhiyun #include "malidp_drv.h"
19*4882a593Smuzhiyun #include "malidp_hw.h"
20*4882a593Smuzhiyun #include "malidp_mw.h"
21*4882a593Smuzhiyun
22*4882a593Smuzhiyun #define to_mw_state(_state) (struct malidp_mw_connector_state *)(_state)
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun struct malidp_mw_connector_state {
25*4882a593Smuzhiyun struct drm_connector_state base;
26*4882a593Smuzhiyun dma_addr_t addrs[2];
27*4882a593Smuzhiyun s32 pitches[2];
28*4882a593Smuzhiyun u8 format;
29*4882a593Smuzhiyun u8 n_planes;
30*4882a593Smuzhiyun bool rgb2yuv_initialized;
31*4882a593Smuzhiyun const s16 *rgb2yuv_coeffs;
32*4882a593Smuzhiyun };
33*4882a593Smuzhiyun
malidp_mw_connector_get_modes(struct drm_connector * connector)34*4882a593Smuzhiyun static int malidp_mw_connector_get_modes(struct drm_connector *connector)
35*4882a593Smuzhiyun {
36*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun return drm_add_modes_noedid(connector, dev->mode_config.max_width,
39*4882a593Smuzhiyun dev->mode_config.max_height);
40*4882a593Smuzhiyun }
41*4882a593Smuzhiyun
42*4882a593Smuzhiyun static enum drm_mode_status
malidp_mw_connector_mode_valid(struct drm_connector * connector,struct drm_display_mode * mode)43*4882a593Smuzhiyun malidp_mw_connector_mode_valid(struct drm_connector *connector,
44*4882a593Smuzhiyun struct drm_display_mode *mode)
45*4882a593Smuzhiyun {
46*4882a593Smuzhiyun struct drm_device *dev = connector->dev;
47*4882a593Smuzhiyun struct drm_mode_config *mode_config = &dev->mode_config;
48*4882a593Smuzhiyun int w = mode->hdisplay, h = mode->vdisplay;
49*4882a593Smuzhiyun
50*4882a593Smuzhiyun if ((w < mode_config->min_width) || (w > mode_config->max_width))
51*4882a593Smuzhiyun return MODE_BAD_HVALUE;
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun if ((h < mode_config->min_height) || (h > mode_config->max_height))
54*4882a593Smuzhiyun return MODE_BAD_VVALUE;
55*4882a593Smuzhiyun
56*4882a593Smuzhiyun return MODE_OK;
57*4882a593Smuzhiyun }
58*4882a593Smuzhiyun
59*4882a593Smuzhiyun static const struct drm_connector_helper_funcs malidp_mw_connector_helper_funcs = {
60*4882a593Smuzhiyun .get_modes = malidp_mw_connector_get_modes,
61*4882a593Smuzhiyun .mode_valid = malidp_mw_connector_mode_valid,
62*4882a593Smuzhiyun };
63*4882a593Smuzhiyun
malidp_mw_connector_reset(struct drm_connector * connector)64*4882a593Smuzhiyun static void malidp_mw_connector_reset(struct drm_connector *connector)
65*4882a593Smuzhiyun {
66*4882a593Smuzhiyun struct malidp_mw_connector_state *mw_state =
67*4882a593Smuzhiyun kzalloc(sizeof(*mw_state), GFP_KERNEL);
68*4882a593Smuzhiyun
69*4882a593Smuzhiyun if (connector->state)
70*4882a593Smuzhiyun __drm_atomic_helper_connector_destroy_state(connector->state);
71*4882a593Smuzhiyun
72*4882a593Smuzhiyun kfree(connector->state);
73*4882a593Smuzhiyun __drm_atomic_helper_connector_reset(connector, &mw_state->base);
74*4882a593Smuzhiyun }
75*4882a593Smuzhiyun
76*4882a593Smuzhiyun static enum drm_connector_status
malidp_mw_connector_detect(struct drm_connector * connector,bool force)77*4882a593Smuzhiyun malidp_mw_connector_detect(struct drm_connector *connector, bool force)
78*4882a593Smuzhiyun {
79*4882a593Smuzhiyun return connector_status_connected;
80*4882a593Smuzhiyun }
81*4882a593Smuzhiyun
malidp_mw_connector_destroy(struct drm_connector * connector)82*4882a593Smuzhiyun static void malidp_mw_connector_destroy(struct drm_connector *connector)
83*4882a593Smuzhiyun {
84*4882a593Smuzhiyun drm_connector_cleanup(connector);
85*4882a593Smuzhiyun }
86*4882a593Smuzhiyun
87*4882a593Smuzhiyun static struct drm_connector_state *
malidp_mw_connector_duplicate_state(struct drm_connector * connector)88*4882a593Smuzhiyun malidp_mw_connector_duplicate_state(struct drm_connector *connector)
89*4882a593Smuzhiyun {
90*4882a593Smuzhiyun struct malidp_mw_connector_state *mw_state, *mw_current_state;
91*4882a593Smuzhiyun
92*4882a593Smuzhiyun if (WARN_ON(!connector->state))
93*4882a593Smuzhiyun return NULL;
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun mw_state = kzalloc(sizeof(*mw_state), GFP_KERNEL);
96*4882a593Smuzhiyun if (!mw_state)
97*4882a593Smuzhiyun return NULL;
98*4882a593Smuzhiyun
99*4882a593Smuzhiyun mw_current_state = to_mw_state(connector->state);
100*4882a593Smuzhiyun mw_state->rgb2yuv_coeffs = mw_current_state->rgb2yuv_coeffs;
101*4882a593Smuzhiyun mw_state->rgb2yuv_initialized = mw_current_state->rgb2yuv_initialized;
102*4882a593Smuzhiyun
103*4882a593Smuzhiyun __drm_atomic_helper_connector_duplicate_state(connector, &mw_state->base);
104*4882a593Smuzhiyun
105*4882a593Smuzhiyun return &mw_state->base;
106*4882a593Smuzhiyun }
107*4882a593Smuzhiyun
108*4882a593Smuzhiyun static const struct drm_connector_funcs malidp_mw_connector_funcs = {
109*4882a593Smuzhiyun .reset = malidp_mw_connector_reset,
110*4882a593Smuzhiyun .detect = malidp_mw_connector_detect,
111*4882a593Smuzhiyun .fill_modes = drm_helper_probe_single_connector_modes,
112*4882a593Smuzhiyun .destroy = malidp_mw_connector_destroy,
113*4882a593Smuzhiyun .atomic_duplicate_state = malidp_mw_connector_duplicate_state,
114*4882a593Smuzhiyun .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
115*4882a593Smuzhiyun };
116*4882a593Smuzhiyun
117*4882a593Smuzhiyun static const s16 rgb2yuv_coeffs_bt709_limited[MALIDP_COLORADJ_NUM_COEFFS] = {
118*4882a593Smuzhiyun 47, 157, 16,
119*4882a593Smuzhiyun -26, -87, 112,
120*4882a593Smuzhiyun 112, -102, -10,
121*4882a593Smuzhiyun 16, 128, 128
122*4882a593Smuzhiyun };
123*4882a593Smuzhiyun
124*4882a593Smuzhiyun static int
malidp_mw_encoder_atomic_check(struct drm_encoder * encoder,struct drm_crtc_state * crtc_state,struct drm_connector_state * conn_state)125*4882a593Smuzhiyun malidp_mw_encoder_atomic_check(struct drm_encoder *encoder,
126*4882a593Smuzhiyun struct drm_crtc_state *crtc_state,
127*4882a593Smuzhiyun struct drm_connector_state *conn_state)
128*4882a593Smuzhiyun {
129*4882a593Smuzhiyun struct malidp_mw_connector_state *mw_state = to_mw_state(conn_state);
130*4882a593Smuzhiyun struct malidp_drm *malidp = encoder->dev->dev_private;
131*4882a593Smuzhiyun struct drm_framebuffer *fb;
132*4882a593Smuzhiyun int i, n_planes;
133*4882a593Smuzhiyun
134*4882a593Smuzhiyun if (!conn_state->writeback_job)
135*4882a593Smuzhiyun return 0;
136*4882a593Smuzhiyun
137*4882a593Smuzhiyun fb = conn_state->writeback_job->fb;
138*4882a593Smuzhiyun if ((fb->width != crtc_state->mode.hdisplay) ||
139*4882a593Smuzhiyun (fb->height != crtc_state->mode.vdisplay)) {
140*4882a593Smuzhiyun DRM_DEBUG_KMS("Invalid framebuffer size %ux%u\n",
141*4882a593Smuzhiyun fb->width, fb->height);
142*4882a593Smuzhiyun return -EINVAL;
143*4882a593Smuzhiyun }
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun if (fb->modifier) {
146*4882a593Smuzhiyun DRM_DEBUG_KMS("Writeback framebuffer does not support modifiers\n");
147*4882a593Smuzhiyun return -EINVAL;
148*4882a593Smuzhiyun }
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun mw_state->format =
151*4882a593Smuzhiyun malidp_hw_get_format_id(&malidp->dev->hw->map, SE_MEMWRITE,
152*4882a593Smuzhiyun fb->format->format, !!fb->modifier);
153*4882a593Smuzhiyun if (mw_state->format == MALIDP_INVALID_FORMAT_ID) {
154*4882a593Smuzhiyun struct drm_format_name_buf format_name;
155*4882a593Smuzhiyun
156*4882a593Smuzhiyun DRM_DEBUG_KMS("Invalid pixel format %s\n",
157*4882a593Smuzhiyun drm_get_format_name(fb->format->format,
158*4882a593Smuzhiyun &format_name));
159*4882a593Smuzhiyun return -EINVAL;
160*4882a593Smuzhiyun }
161*4882a593Smuzhiyun
162*4882a593Smuzhiyun n_planes = fb->format->num_planes;
163*4882a593Smuzhiyun for (i = 0; i < n_planes; i++) {
164*4882a593Smuzhiyun struct drm_gem_cma_object *obj = drm_fb_cma_get_gem_obj(fb, i);
165*4882a593Smuzhiyun /* memory write buffers are never rotated */
166*4882a593Smuzhiyun u8 alignment = malidp_hw_get_pitch_align(malidp->dev, 0);
167*4882a593Smuzhiyun
168*4882a593Smuzhiyun if (fb->pitches[i] & (alignment - 1)) {
169*4882a593Smuzhiyun DRM_DEBUG_KMS("Invalid pitch %u for plane %d\n",
170*4882a593Smuzhiyun fb->pitches[i], i);
171*4882a593Smuzhiyun return -EINVAL;
172*4882a593Smuzhiyun }
173*4882a593Smuzhiyun mw_state->pitches[i] = fb->pitches[i];
174*4882a593Smuzhiyun mw_state->addrs[i] = obj->paddr + fb->offsets[i];
175*4882a593Smuzhiyun }
176*4882a593Smuzhiyun mw_state->n_planes = n_planes;
177*4882a593Smuzhiyun
178*4882a593Smuzhiyun if (fb->format->is_yuv)
179*4882a593Smuzhiyun mw_state->rgb2yuv_coeffs = rgb2yuv_coeffs_bt709_limited;
180*4882a593Smuzhiyun
181*4882a593Smuzhiyun return 0;
182*4882a593Smuzhiyun }
183*4882a593Smuzhiyun
184*4882a593Smuzhiyun static const struct drm_encoder_helper_funcs malidp_mw_encoder_helper_funcs = {
185*4882a593Smuzhiyun .atomic_check = malidp_mw_encoder_atomic_check,
186*4882a593Smuzhiyun };
187*4882a593Smuzhiyun
get_writeback_formats(struct malidp_drm * malidp,int * n_formats)188*4882a593Smuzhiyun static u32 *get_writeback_formats(struct malidp_drm *malidp, int *n_formats)
189*4882a593Smuzhiyun {
190*4882a593Smuzhiyun const struct malidp_hw_regmap *map = &malidp->dev->hw->map;
191*4882a593Smuzhiyun u32 *formats;
192*4882a593Smuzhiyun int n, i;
193*4882a593Smuzhiyun
194*4882a593Smuzhiyun formats = kcalloc(map->n_pixel_formats, sizeof(*formats),
195*4882a593Smuzhiyun GFP_KERNEL);
196*4882a593Smuzhiyun if (!formats)
197*4882a593Smuzhiyun return NULL;
198*4882a593Smuzhiyun
199*4882a593Smuzhiyun for (n = 0, i = 0; i < map->n_pixel_formats; i++) {
200*4882a593Smuzhiyun if (map->pixel_formats[i].layer & SE_MEMWRITE)
201*4882a593Smuzhiyun formats[n++] = map->pixel_formats[i].format;
202*4882a593Smuzhiyun }
203*4882a593Smuzhiyun
204*4882a593Smuzhiyun *n_formats = n;
205*4882a593Smuzhiyun
206*4882a593Smuzhiyun return formats;
207*4882a593Smuzhiyun }
208*4882a593Smuzhiyun
malidp_mw_connector_init(struct drm_device * drm)209*4882a593Smuzhiyun int malidp_mw_connector_init(struct drm_device *drm)
210*4882a593Smuzhiyun {
211*4882a593Smuzhiyun struct malidp_drm *malidp = drm->dev_private;
212*4882a593Smuzhiyun u32 *formats;
213*4882a593Smuzhiyun int ret, n_formats;
214*4882a593Smuzhiyun
215*4882a593Smuzhiyun if (!malidp->dev->hw->enable_memwrite)
216*4882a593Smuzhiyun return 0;
217*4882a593Smuzhiyun
218*4882a593Smuzhiyun malidp->mw_connector.encoder.possible_crtcs = 1 << drm_crtc_index(&malidp->crtc);
219*4882a593Smuzhiyun drm_connector_helper_add(&malidp->mw_connector.base,
220*4882a593Smuzhiyun &malidp_mw_connector_helper_funcs);
221*4882a593Smuzhiyun
222*4882a593Smuzhiyun formats = get_writeback_formats(malidp, &n_formats);
223*4882a593Smuzhiyun if (!formats)
224*4882a593Smuzhiyun return -ENOMEM;
225*4882a593Smuzhiyun
226*4882a593Smuzhiyun ret = drm_writeback_connector_init(drm, &malidp->mw_connector,
227*4882a593Smuzhiyun &malidp_mw_connector_funcs,
228*4882a593Smuzhiyun &malidp_mw_encoder_helper_funcs,
229*4882a593Smuzhiyun formats, n_formats);
230*4882a593Smuzhiyun kfree(formats);
231*4882a593Smuzhiyun if (ret)
232*4882a593Smuzhiyun return ret;
233*4882a593Smuzhiyun
234*4882a593Smuzhiyun return 0;
235*4882a593Smuzhiyun }
236*4882a593Smuzhiyun
malidp_mw_atomic_commit(struct drm_device * drm,struct drm_atomic_state * old_state)237*4882a593Smuzhiyun void malidp_mw_atomic_commit(struct drm_device *drm,
238*4882a593Smuzhiyun struct drm_atomic_state *old_state)
239*4882a593Smuzhiyun {
240*4882a593Smuzhiyun struct malidp_drm *malidp = drm->dev_private;
241*4882a593Smuzhiyun struct drm_writeback_connector *mw_conn = &malidp->mw_connector;
242*4882a593Smuzhiyun struct drm_connector_state *conn_state = mw_conn->base.state;
243*4882a593Smuzhiyun struct malidp_hw_device *hwdev = malidp->dev;
244*4882a593Smuzhiyun struct malidp_mw_connector_state *mw_state;
245*4882a593Smuzhiyun
246*4882a593Smuzhiyun if (!conn_state)
247*4882a593Smuzhiyun return;
248*4882a593Smuzhiyun
249*4882a593Smuzhiyun mw_state = to_mw_state(conn_state);
250*4882a593Smuzhiyun
251*4882a593Smuzhiyun if (conn_state->writeback_job) {
252*4882a593Smuzhiyun struct drm_framebuffer *fb = conn_state->writeback_job->fb;
253*4882a593Smuzhiyun
254*4882a593Smuzhiyun DRM_DEV_DEBUG_DRIVER(drm->dev,
255*4882a593Smuzhiyun "Enable memwrite %ux%u:%d %pad fmt: %u\n",
256*4882a593Smuzhiyun fb->width, fb->height,
257*4882a593Smuzhiyun mw_state->pitches[0],
258*4882a593Smuzhiyun &mw_state->addrs[0],
259*4882a593Smuzhiyun mw_state->format);
260*4882a593Smuzhiyun
261*4882a593Smuzhiyun drm_writeback_queue_job(mw_conn, conn_state);
262*4882a593Smuzhiyun hwdev->hw->enable_memwrite(hwdev, mw_state->addrs,
263*4882a593Smuzhiyun mw_state->pitches, mw_state->n_planes,
264*4882a593Smuzhiyun fb->width, fb->height, mw_state->format,
265*4882a593Smuzhiyun !mw_state->rgb2yuv_initialized ?
266*4882a593Smuzhiyun mw_state->rgb2yuv_coeffs : NULL);
267*4882a593Smuzhiyun mw_state->rgb2yuv_initialized = !!mw_state->rgb2yuv_coeffs;
268*4882a593Smuzhiyun } else {
269*4882a593Smuzhiyun DRM_DEV_DEBUG_DRIVER(drm->dev, "Disable memwrite\n");
270*4882a593Smuzhiyun hwdev->hw->disable_memwrite(hwdev);
271*4882a593Smuzhiyun }
272*4882a593Smuzhiyun }
273