1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0 */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ARM HDLCD Controller register definition 4*4882a593Smuzhiyun */ 5*4882a593Smuzhiyun 6*4882a593Smuzhiyun #ifndef __HDLCD_DRV_H__ 7*4882a593Smuzhiyun #define __HDLCD_DRV_H__ 8*4882a593Smuzhiyun 9*4882a593Smuzhiyun struct hdlcd_drm_private { 10*4882a593Smuzhiyun void __iomem *mmio; 11*4882a593Smuzhiyun struct clk *clk; 12*4882a593Smuzhiyun struct drm_crtc crtc; 13*4882a593Smuzhiyun struct drm_plane *plane; 14*4882a593Smuzhiyun #ifdef CONFIG_DEBUG_FS 15*4882a593Smuzhiyun atomic_t buffer_underrun_count; 16*4882a593Smuzhiyun atomic_t bus_error_count; 17*4882a593Smuzhiyun atomic_t vsync_count; 18*4882a593Smuzhiyun atomic_t dma_end_count; 19*4882a593Smuzhiyun #endif 20*4882a593Smuzhiyun }; 21*4882a593Smuzhiyun 22*4882a593Smuzhiyun #define crtc_to_hdlcd_priv(x) container_of(x, struct hdlcd_drm_private, crtc) 23*4882a593Smuzhiyun hdlcd_write(struct hdlcd_drm_private * hdlcd,unsigned int reg,u32 value)24*4882a593Smuzhiyunstatic inline void hdlcd_write(struct hdlcd_drm_private *hdlcd, 25*4882a593Smuzhiyun unsigned int reg, u32 value) 26*4882a593Smuzhiyun { 27*4882a593Smuzhiyun writel(value, hdlcd->mmio + reg); 28*4882a593Smuzhiyun } 29*4882a593Smuzhiyun hdlcd_read(struct hdlcd_drm_private * hdlcd,unsigned int reg)30*4882a593Smuzhiyunstatic inline u32 hdlcd_read(struct hdlcd_drm_private *hdlcd, unsigned int reg) 31*4882a593Smuzhiyun { 32*4882a593Smuzhiyun return readl(hdlcd->mmio + reg); 33*4882a593Smuzhiyun } 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun int hdlcd_setup_crtc(struct drm_device *dev); 36*4882a593Smuzhiyun void hdlcd_set_scanout(struct hdlcd_drm_private *hdlcd); 37*4882a593Smuzhiyun 38*4882a593Smuzhiyun #endif /* __HDLCD_DRV_H__ */ 39