1*4882a593Smuzhiyun /* SPDX-License-Identifier: GPL-2.0-only */ 2*4882a593Smuzhiyun /* 3*4882a593Smuzhiyun * ARC PGU DRM driver. 4*4882a593Smuzhiyun * 5*4882a593Smuzhiyun * Copyright (C) 2016 Synopsys, Inc. (www.synopsys.com) 6*4882a593Smuzhiyun */ 7*4882a593Smuzhiyun 8*4882a593Smuzhiyun #ifndef _ARC_PGU_REGS_H_ 9*4882a593Smuzhiyun #define _ARC_PGU_REGS_H_ 10*4882a593Smuzhiyun 11*4882a593Smuzhiyun #define ARCPGU_REG_CTRL 0x00 12*4882a593Smuzhiyun #define ARCPGU_REG_STAT 0x04 13*4882a593Smuzhiyun #define ARCPGU_REG_FMT 0x10 14*4882a593Smuzhiyun #define ARCPGU_REG_HSYNC 0x14 15*4882a593Smuzhiyun #define ARCPGU_REG_VSYNC 0x18 16*4882a593Smuzhiyun #define ARCPGU_REG_ACTIVE 0x1c 17*4882a593Smuzhiyun #define ARCPGU_REG_BUF0_ADDR 0x40 18*4882a593Smuzhiyun #define ARCPGU_REG_STRIDE 0x50 19*4882a593Smuzhiyun #define ARCPGU_REG_START_SET 0x84 20*4882a593Smuzhiyun 21*4882a593Smuzhiyun #define ARCPGU_REG_ID 0x3FC 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #define ARCPGU_CTRL_ENABLE_MASK 0x02 24*4882a593Smuzhiyun #define ARCPGU_CTRL_VS_POL_MASK 0x1 25*4882a593Smuzhiyun #define ARCPGU_CTRL_VS_POL_OFST 0x3 26*4882a593Smuzhiyun #define ARCPGU_CTRL_HS_POL_MASK 0x1 27*4882a593Smuzhiyun #define ARCPGU_CTRL_HS_POL_OFST 0x4 28*4882a593Smuzhiyun #define ARCPGU_MODE_XRGB8888 BIT(2) 29*4882a593Smuzhiyun #define ARCPGU_STAT_BUSY_MASK 0x02 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #endif 32