1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #ifndef _SMUMGR_H_ 24*4882a593Smuzhiyun #define _SMUMGR_H_ 25*4882a593Smuzhiyun #include <linux/types.h> 26*4882a593Smuzhiyun #include "amd_powerplay.h" 27*4882a593Smuzhiyun #include "hwmgr.h" 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun enum SMU_TABLE { 30*4882a593Smuzhiyun SMU_UVD_TABLE = 0, 31*4882a593Smuzhiyun SMU_VCE_TABLE, 32*4882a593Smuzhiyun SMU_BIF_TABLE, 33*4882a593Smuzhiyun }; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun enum SMU_TYPE { 36*4882a593Smuzhiyun SMU_SoftRegisters = 0, 37*4882a593Smuzhiyun SMU_Discrete_DpmTable, 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun enum SMU_MEMBER { 41*4882a593Smuzhiyun HandshakeDisables = 0, 42*4882a593Smuzhiyun VoltageChangeTimeout, 43*4882a593Smuzhiyun AverageGraphicsActivity, 44*4882a593Smuzhiyun AverageMemoryActivity, 45*4882a593Smuzhiyun PreVBlankGap, 46*4882a593Smuzhiyun VBlankTimeout, 47*4882a593Smuzhiyun UcodeLoadStatus, 48*4882a593Smuzhiyun UvdBootLevel, 49*4882a593Smuzhiyun VceBootLevel, 50*4882a593Smuzhiyun LowSclkInterruptThreshold, 51*4882a593Smuzhiyun DRAM_LOG_ADDR_H, 52*4882a593Smuzhiyun DRAM_LOG_ADDR_L, 53*4882a593Smuzhiyun DRAM_LOG_PHY_ADDR_H, 54*4882a593Smuzhiyun DRAM_LOG_PHY_ADDR_L, 55*4882a593Smuzhiyun DRAM_LOG_BUFF_SIZE, 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun enum SMU_MAC_DEFINITION { 60*4882a593Smuzhiyun SMU_MAX_LEVELS_GRAPHICS = 0, 61*4882a593Smuzhiyun SMU_MAX_LEVELS_MEMORY, 62*4882a593Smuzhiyun SMU_MAX_LEVELS_LINK, 63*4882a593Smuzhiyun SMU_MAX_ENTRIES_SMIO, 64*4882a593Smuzhiyun SMU_MAX_LEVELS_VDDC, 65*4882a593Smuzhiyun SMU_MAX_LEVELS_VDDGFX, 66*4882a593Smuzhiyun SMU_MAX_LEVELS_VDDCI, 67*4882a593Smuzhiyun SMU_MAX_LEVELS_MVDD, 68*4882a593Smuzhiyun SMU_UVD_MCLK_HANDSHAKE_DISABLE, 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun enum SMU9_TABLE_ID { 72*4882a593Smuzhiyun PPTABLE = 0, 73*4882a593Smuzhiyun WMTABLE, 74*4882a593Smuzhiyun AVFSTABLE, 75*4882a593Smuzhiyun TOOLSTABLE, 76*4882a593Smuzhiyun AVFSFUSETABLE 77*4882a593Smuzhiyun }; 78*4882a593Smuzhiyun 79*4882a593Smuzhiyun enum SMU10_TABLE_ID { 80*4882a593Smuzhiyun SMU10_WMTABLE = 0, 81*4882a593Smuzhiyun SMU10_CLOCKTABLE, 82*4882a593Smuzhiyun }; 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun extern int smum_download_powerplay_table(struct pp_hwmgr *hwmgr, void **table); 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun extern int smum_upload_powerplay_table(struct pp_hwmgr *hwmgr); 87*4882a593Smuzhiyun 88*4882a593Smuzhiyun extern int smum_send_msg_to_smc(struct pp_hwmgr *hwmgr, uint16_t msg, uint32_t *resp); 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun extern int smum_send_msg_to_smc_with_parameter(struct pp_hwmgr *hwmgr, 91*4882a593Smuzhiyun uint16_t msg, uint32_t parameter, 92*4882a593Smuzhiyun uint32_t *resp); 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun extern int smum_update_sclk_threshold(struct pp_hwmgr *hwmgr); 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun extern int smum_update_smc_table(struct pp_hwmgr *hwmgr, uint32_t type); 97*4882a593Smuzhiyun extern int smum_process_firmware_header(struct pp_hwmgr *hwmgr); 98*4882a593Smuzhiyun extern int smum_thermal_avfs_enable(struct pp_hwmgr *hwmgr); 99*4882a593Smuzhiyun extern int smum_thermal_setup_fan_table(struct pp_hwmgr *hwmgr); 100*4882a593Smuzhiyun extern int smum_init_smc_table(struct pp_hwmgr *hwmgr); 101*4882a593Smuzhiyun extern int smum_populate_all_graphic_levels(struct pp_hwmgr *hwmgr); 102*4882a593Smuzhiyun extern int smum_populate_all_memory_levels(struct pp_hwmgr *hwmgr); 103*4882a593Smuzhiyun extern int smum_initialize_mc_reg_table(struct pp_hwmgr *hwmgr); 104*4882a593Smuzhiyun extern uint32_t smum_get_offsetof(struct pp_hwmgr *hwmgr, 105*4882a593Smuzhiyun uint32_t type, uint32_t member); 106*4882a593Smuzhiyun extern uint32_t smum_get_mac_definition(struct pp_hwmgr *hwmgr, uint32_t value); 107*4882a593Smuzhiyun 108*4882a593Smuzhiyun extern bool smum_is_dpm_running(struct pp_hwmgr *hwmgr); 109*4882a593Smuzhiyun 110*4882a593Smuzhiyun extern bool smum_is_hw_avfs_present(struct pp_hwmgr *hwmgr); 111*4882a593Smuzhiyun 112*4882a593Smuzhiyun extern int smum_update_dpm_settings(struct pp_hwmgr *hwmgr, void *profile_setting); 113*4882a593Smuzhiyun 114*4882a593Smuzhiyun extern int smum_smc_table_manager(struct pp_hwmgr *hwmgr, uint8_t *table, uint16_t table_id, bool rw); 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun extern int smum_stop_smc(struct pp_hwmgr *hwmgr); 117*4882a593Smuzhiyun 118*4882a593Smuzhiyun #endif 119