1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2015 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifndef __AMD_PCIE_H__ 24*4882a593Smuzhiyun #define __AMD_PCIE_H__ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* Following flags shows PCIe link speed supported in driver which are decided by chipset and ASIC */ 27*4882a593Smuzhiyun #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00010000 28*4882a593Smuzhiyun #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00020000 29*4882a593Smuzhiyun #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00040000 30*4882a593Smuzhiyun #define CAIL_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00080000 31*4882a593Smuzhiyun #define CAIL_PCIE_LINK_SPEED_SUPPORT_MASK 0xFFFF0000 32*4882a593Smuzhiyun #define CAIL_PCIE_LINK_SPEED_SUPPORT_SHIFT 16 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun /* Following flags shows PCIe link speed supported by ASIC H/W.*/ 35*4882a593Smuzhiyun #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 0x00000001 36*4882a593Smuzhiyun #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 0x00000002 37*4882a593Smuzhiyun #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3 0x00000004 38*4882a593Smuzhiyun #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN4 0x00000008 39*4882a593Smuzhiyun #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_MASK 0x0000FFFF 40*4882a593Smuzhiyun #define CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_SHIFT 0 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun /* gen: chipset 1/2, asic 1/2/3 */ 43*4882a593Smuzhiyun #define AMDGPU_DEFAULT_PCIE_GEN_MASK (CAIL_PCIE_LINK_SPEED_SUPPORT_GEN1 \ 44*4882a593Smuzhiyun | CAIL_PCIE_LINK_SPEED_SUPPORT_GEN2 \ 45*4882a593Smuzhiyun | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN1 \ 46*4882a593Smuzhiyun | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN2 \ 47*4882a593Smuzhiyun | CAIL_ASIC_PCIE_LINK_SPEED_SUPPORT_GEN3) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun /* Following flags shows PCIe lane width switch supported in driver which are decided by chipset and ASIC */ 50*4882a593Smuzhiyun #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 0x00010000 51*4882a593Smuzhiyun #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 0x00020000 52*4882a593Smuzhiyun #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 0x00040000 53*4882a593Smuzhiyun #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 0x00080000 54*4882a593Smuzhiyun #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X12 0x00100000 55*4882a593Smuzhiyun #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X16 0x00200000 56*4882a593Smuzhiyun #define CAIL_PCIE_LINK_WIDTH_SUPPORT_X32 0x00400000 57*4882a593Smuzhiyun #define CAIL_PCIE_LINK_WIDTH_SUPPORT_SHIFT 16 58*4882a593Smuzhiyun 59*4882a593Smuzhiyun /* 1/2/4/8/16 lanes */ 60*4882a593Smuzhiyun #define AMDGPU_DEFAULT_PCIE_MLW_MASK (CAIL_PCIE_LINK_WIDTH_SUPPORT_X1 \ 61*4882a593Smuzhiyun | CAIL_PCIE_LINK_WIDTH_SUPPORT_X2 \ 62*4882a593Smuzhiyun | CAIL_PCIE_LINK_WIDTH_SUPPORT_X4 \ 63*4882a593Smuzhiyun | CAIL_PCIE_LINK_WIDTH_SUPPORT_X8 \ 64*4882a593Smuzhiyun | CAIL_PCIE_LINK_WIDTH_SUPPORT_X16) 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun #endif 67