1*4882a593Smuzhiyun# SPDX-License-Identifier: MIT 2*4882a593Smuzhiyunmenu "Display Engine Configuration" 3*4882a593Smuzhiyun depends on DRM && DRM_AMDGPU 4*4882a593Smuzhiyun 5*4882a593Smuzhiyunconfig DRM_AMD_DC 6*4882a593Smuzhiyun bool "AMD DC - Enable new display engine" 7*4882a593Smuzhiyun default y 8*4882a593Smuzhiyun depends on BROKEN || !CC_IS_CLANG || X86_64 || SPARC64 || ARM64 9*4882a593Smuzhiyun select SND_HDA_COMPONENT if SND_HDA_CORE 10*4882a593Smuzhiyun select DRM_AMD_DC_DCN if (X86 || PPC64) && !(KCOV_INSTRUMENT_ALL && KCOV_ENABLE_COMPARISONS) 11*4882a593Smuzhiyun help 12*4882a593Smuzhiyun Choose this option if you want to use the new display engine 13*4882a593Smuzhiyun support for AMDGPU. This adds required support for Vega and 14*4882a593Smuzhiyun Raven ASICs. 15*4882a593Smuzhiyun 16*4882a593Smuzhiyun calculate_bandwidth() is presently broken on all !(X86_64 || SPARC64 || ARM64) 17*4882a593Smuzhiyun architectures built with Clang (all released versions), whereby the stack 18*4882a593Smuzhiyun frame gets blown up to well over 5k. This would cause an immediate kernel 19*4882a593Smuzhiyun panic on most architectures. We'll revert this when the following bug report 20*4882a593Smuzhiyun has been resolved: https://github.com/llvm/llvm-project/issues/41896. 21*4882a593Smuzhiyun 22*4882a593Smuzhiyunconfig DRM_AMD_DC_DCN 23*4882a593Smuzhiyun def_bool n 24*4882a593Smuzhiyun help 25*4882a593Smuzhiyun Raven, Navi and Renoir family support for display engine 26*4882a593Smuzhiyun 27*4882a593Smuzhiyunconfig DRM_AMD_DC_DCN3_0 28*4882a593Smuzhiyun bool "DCN 3.0 family" 29*4882a593Smuzhiyun depends on DRM_AMD_DC && X86 30*4882a593Smuzhiyun depends on DRM_AMD_DC_DCN 31*4882a593Smuzhiyun help 32*4882a593Smuzhiyun Choose this option if you want to have 33*4882a593Smuzhiyun sienna_cichlid support for display engine 34*4882a593Smuzhiyun 35*4882a593Smuzhiyunconfig DRM_AMD_DC_HDCP 36*4882a593Smuzhiyun bool "Enable HDCP support in DC" 37*4882a593Smuzhiyun depends on DRM_AMD_DC 38*4882a593Smuzhiyun help 39*4882a593Smuzhiyun Choose this option if you want to support HDCP authentication. 40*4882a593Smuzhiyun 41*4882a593Smuzhiyunconfig DRM_AMD_DC_SI 42*4882a593Smuzhiyun bool "AMD DC support for Southern Islands ASICs" 43*4882a593Smuzhiyun depends on DRM_AMDGPU_SI 44*4882a593Smuzhiyun depends on DRM_AMD_DC 45*4882a593Smuzhiyun default n 46*4882a593Smuzhiyun help 47*4882a593Smuzhiyun Choose this option to enable new AMD DC support for SI asics 48*4882a593Smuzhiyun by default. This includes Tahiti, Pitcairn, Cape Verde, Oland. 49*4882a593Smuzhiyun Hainan is not supported by AMD DC and it has no physical DCE6. 50*4882a593Smuzhiyun 51*4882a593Smuzhiyunconfig DEBUG_KERNEL_DC 52*4882a593Smuzhiyun bool "Enable kgdb break in DC" 53*4882a593Smuzhiyun depends on DRM_AMD_DC 54*4882a593Smuzhiyun depends on KGDB 55*4882a593Smuzhiyun help 56*4882a593Smuzhiyun Choose this option if you want to hit kdgb_break in assert. 57*4882a593Smuzhiyun 58*4882a593Smuzhiyunendmenu 59