1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifndef __KFD_TOPOLOGY_H__ 24*4882a593Smuzhiyun #define __KFD_TOPOLOGY_H__ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #include <linux/types.h> 27*4882a593Smuzhiyun #include <linux/list.h> 28*4882a593Smuzhiyun #include "kfd_crat.h" 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define KFD_TOPOLOGY_PUBLIC_NAME_SIZE 32 31*4882a593Smuzhiyun 32*4882a593Smuzhiyun #define HSA_CAP_HOT_PLUGGABLE 0x00000001 33*4882a593Smuzhiyun #define HSA_CAP_ATS_PRESENT 0x00000002 34*4882a593Smuzhiyun #define HSA_CAP_SHARED_WITH_GRAPHICS 0x00000004 35*4882a593Smuzhiyun #define HSA_CAP_QUEUE_SIZE_POW2 0x00000008 36*4882a593Smuzhiyun #define HSA_CAP_QUEUE_SIZE_32BIT 0x00000010 37*4882a593Smuzhiyun #define HSA_CAP_QUEUE_IDLE_EVENT 0x00000020 38*4882a593Smuzhiyun #define HSA_CAP_VA_LIMIT 0x00000040 39*4882a593Smuzhiyun #define HSA_CAP_WATCH_POINTS_SUPPORTED 0x00000080 40*4882a593Smuzhiyun #define HSA_CAP_WATCH_POINTS_TOTALBITS_MASK 0x00000f00 41*4882a593Smuzhiyun #define HSA_CAP_WATCH_POINTS_TOTALBITS_SHIFT 8 42*4882a593Smuzhiyun #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_MASK 0x00003000 43*4882a593Smuzhiyun #define HSA_CAP_DOORBELL_TYPE_TOTALBITS_SHIFT 12 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define HSA_CAP_DOORBELL_TYPE_PRE_1_0 0x0 46*4882a593Smuzhiyun #define HSA_CAP_DOORBELL_TYPE_1_0 0x1 47*4882a593Smuzhiyun #define HSA_CAP_DOORBELL_TYPE_2_0 0x2 48*4882a593Smuzhiyun #define HSA_CAP_AQL_QUEUE_DOUBLE_MAP 0x00004000 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun #define HSA_CAP_SRAM_EDCSUPPORTED 0x00080000 51*4882a593Smuzhiyun #define HSA_CAP_MEM_EDCSUPPORTED 0x00100000 52*4882a593Smuzhiyun #define HSA_CAP_RASEVENTNOTIFY 0x00200000 53*4882a593Smuzhiyun #define HSA_CAP_ASIC_REVISION_MASK 0x03c00000 54*4882a593Smuzhiyun #define HSA_CAP_ASIC_REVISION_SHIFT 22 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun #define HSA_CAP_RESERVED 0xfc078000 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun struct kfd_node_properties { 59*4882a593Smuzhiyun uint64_t hive_id; 60*4882a593Smuzhiyun uint64_t unique_id; 61*4882a593Smuzhiyun uint32_t cpu_cores_count; 62*4882a593Smuzhiyun uint32_t simd_count; 63*4882a593Smuzhiyun uint32_t mem_banks_count; 64*4882a593Smuzhiyun uint32_t caches_count; 65*4882a593Smuzhiyun uint32_t io_links_count; 66*4882a593Smuzhiyun uint32_t cpu_core_id_base; 67*4882a593Smuzhiyun uint32_t simd_id_base; 68*4882a593Smuzhiyun uint32_t capability; 69*4882a593Smuzhiyun uint32_t max_waves_per_simd; 70*4882a593Smuzhiyun uint32_t lds_size_in_kb; 71*4882a593Smuzhiyun uint32_t gds_size_in_kb; 72*4882a593Smuzhiyun uint32_t num_gws; 73*4882a593Smuzhiyun uint32_t wave_front_size; 74*4882a593Smuzhiyun uint32_t array_count; 75*4882a593Smuzhiyun uint32_t simd_arrays_per_engine; 76*4882a593Smuzhiyun uint32_t cu_per_simd_array; 77*4882a593Smuzhiyun uint32_t simd_per_cu; 78*4882a593Smuzhiyun uint32_t max_slots_scratch_cu; 79*4882a593Smuzhiyun uint32_t engine_id; 80*4882a593Smuzhiyun uint32_t vendor_id; 81*4882a593Smuzhiyun uint32_t device_id; 82*4882a593Smuzhiyun uint32_t location_id; 83*4882a593Smuzhiyun uint32_t domain; 84*4882a593Smuzhiyun uint32_t max_engine_clk_fcompute; 85*4882a593Smuzhiyun uint32_t max_engine_clk_ccompute; 86*4882a593Smuzhiyun int32_t drm_render_minor; 87*4882a593Smuzhiyun uint32_t num_sdma_engines; 88*4882a593Smuzhiyun uint32_t num_sdma_xgmi_engines; 89*4882a593Smuzhiyun uint32_t num_sdma_queues_per_engine; 90*4882a593Smuzhiyun uint32_t num_cp_queues; 91*4882a593Smuzhiyun char name[KFD_TOPOLOGY_PUBLIC_NAME_SIZE]; 92*4882a593Smuzhiyun }; 93*4882a593Smuzhiyun 94*4882a593Smuzhiyun #define HSA_MEM_HEAP_TYPE_SYSTEM 0 95*4882a593Smuzhiyun #define HSA_MEM_HEAP_TYPE_FB_PUBLIC 1 96*4882a593Smuzhiyun #define HSA_MEM_HEAP_TYPE_FB_PRIVATE 2 97*4882a593Smuzhiyun #define HSA_MEM_HEAP_TYPE_GPU_GDS 3 98*4882a593Smuzhiyun #define HSA_MEM_HEAP_TYPE_GPU_LDS 4 99*4882a593Smuzhiyun #define HSA_MEM_HEAP_TYPE_GPU_SCRATCH 5 100*4882a593Smuzhiyun 101*4882a593Smuzhiyun #define HSA_MEM_FLAGS_HOT_PLUGGABLE 0x00000001 102*4882a593Smuzhiyun #define HSA_MEM_FLAGS_NON_VOLATILE 0x00000002 103*4882a593Smuzhiyun #define HSA_MEM_FLAGS_RESERVED 0xfffffffc 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun struct kfd_mem_properties { 106*4882a593Smuzhiyun struct list_head list; 107*4882a593Smuzhiyun uint32_t heap_type; 108*4882a593Smuzhiyun uint64_t size_in_bytes; 109*4882a593Smuzhiyun uint32_t flags; 110*4882a593Smuzhiyun uint32_t width; 111*4882a593Smuzhiyun uint32_t mem_clk_max; 112*4882a593Smuzhiyun struct kfd_dev *gpu; 113*4882a593Smuzhiyun struct kobject *kobj; 114*4882a593Smuzhiyun struct attribute attr; 115*4882a593Smuzhiyun }; 116*4882a593Smuzhiyun 117*4882a593Smuzhiyun #define HSA_CACHE_TYPE_DATA 0x00000001 118*4882a593Smuzhiyun #define HSA_CACHE_TYPE_INSTRUCTION 0x00000002 119*4882a593Smuzhiyun #define HSA_CACHE_TYPE_CPU 0x00000004 120*4882a593Smuzhiyun #define HSA_CACHE_TYPE_HSACU 0x00000008 121*4882a593Smuzhiyun #define HSA_CACHE_TYPE_RESERVED 0xfffffff0 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun struct kfd_cache_properties { 124*4882a593Smuzhiyun struct list_head list; 125*4882a593Smuzhiyun uint32_t processor_id_low; 126*4882a593Smuzhiyun uint32_t cache_level; 127*4882a593Smuzhiyun uint32_t cache_size; 128*4882a593Smuzhiyun uint32_t cacheline_size; 129*4882a593Smuzhiyun uint32_t cachelines_per_tag; 130*4882a593Smuzhiyun uint32_t cache_assoc; 131*4882a593Smuzhiyun uint32_t cache_latency; 132*4882a593Smuzhiyun uint32_t cache_type; 133*4882a593Smuzhiyun uint8_t sibling_map[CRAT_SIBLINGMAP_SIZE]; 134*4882a593Smuzhiyun struct kfd_dev *gpu; 135*4882a593Smuzhiyun struct kobject *kobj; 136*4882a593Smuzhiyun struct attribute attr; 137*4882a593Smuzhiyun }; 138*4882a593Smuzhiyun 139*4882a593Smuzhiyun struct kfd_iolink_properties { 140*4882a593Smuzhiyun struct list_head list; 141*4882a593Smuzhiyun uint32_t iolink_type; 142*4882a593Smuzhiyun uint32_t ver_maj; 143*4882a593Smuzhiyun uint32_t ver_min; 144*4882a593Smuzhiyun uint32_t node_from; 145*4882a593Smuzhiyun uint32_t node_to; 146*4882a593Smuzhiyun uint32_t weight; 147*4882a593Smuzhiyun uint32_t min_latency; 148*4882a593Smuzhiyun uint32_t max_latency; 149*4882a593Smuzhiyun uint32_t min_bandwidth; 150*4882a593Smuzhiyun uint32_t max_bandwidth; 151*4882a593Smuzhiyun uint32_t rec_transfer_size; 152*4882a593Smuzhiyun uint32_t flags; 153*4882a593Smuzhiyun struct kfd_dev *gpu; 154*4882a593Smuzhiyun struct kobject *kobj; 155*4882a593Smuzhiyun struct attribute attr; 156*4882a593Smuzhiyun }; 157*4882a593Smuzhiyun 158*4882a593Smuzhiyun struct kfd_perf_properties { 159*4882a593Smuzhiyun struct list_head list; 160*4882a593Smuzhiyun char block_name[16]; 161*4882a593Smuzhiyun uint32_t max_concurrent; 162*4882a593Smuzhiyun struct attribute_group *attr_group; 163*4882a593Smuzhiyun }; 164*4882a593Smuzhiyun 165*4882a593Smuzhiyun struct kfd_topology_device { 166*4882a593Smuzhiyun struct list_head list; 167*4882a593Smuzhiyun uint32_t gpu_id; 168*4882a593Smuzhiyun uint32_t proximity_domain; 169*4882a593Smuzhiyun struct kfd_node_properties node_props; 170*4882a593Smuzhiyun struct list_head mem_props; 171*4882a593Smuzhiyun uint32_t cache_count; 172*4882a593Smuzhiyun struct list_head cache_props; 173*4882a593Smuzhiyun uint32_t io_link_count; 174*4882a593Smuzhiyun struct list_head io_link_props; 175*4882a593Smuzhiyun struct list_head perf_props; 176*4882a593Smuzhiyun struct kfd_dev *gpu; 177*4882a593Smuzhiyun struct kobject *kobj_node; 178*4882a593Smuzhiyun struct kobject *kobj_mem; 179*4882a593Smuzhiyun struct kobject *kobj_cache; 180*4882a593Smuzhiyun struct kobject *kobj_iolink; 181*4882a593Smuzhiyun struct kobject *kobj_perf; 182*4882a593Smuzhiyun struct attribute attr_gpuid; 183*4882a593Smuzhiyun struct attribute attr_name; 184*4882a593Smuzhiyun struct attribute attr_props; 185*4882a593Smuzhiyun uint8_t oem_id[CRAT_OEMID_LENGTH]; 186*4882a593Smuzhiyun uint8_t oem_table_id[CRAT_OEMTABLEID_LENGTH]; 187*4882a593Smuzhiyun uint32_t oem_revision; 188*4882a593Smuzhiyun }; 189*4882a593Smuzhiyun 190*4882a593Smuzhiyun struct kfd_system_properties { 191*4882a593Smuzhiyun uint32_t num_devices; /* Number of H-NUMA nodes */ 192*4882a593Smuzhiyun uint32_t generation_count; 193*4882a593Smuzhiyun uint64_t platform_oem; 194*4882a593Smuzhiyun uint64_t platform_id; 195*4882a593Smuzhiyun uint64_t platform_rev; 196*4882a593Smuzhiyun struct kobject *kobj_topology; 197*4882a593Smuzhiyun struct kobject *kobj_nodes; 198*4882a593Smuzhiyun struct attribute attr_genid; 199*4882a593Smuzhiyun struct attribute attr_props; 200*4882a593Smuzhiyun }; 201*4882a593Smuzhiyun 202*4882a593Smuzhiyun struct kfd_topology_device *kfd_create_topology_device( 203*4882a593Smuzhiyun struct list_head *device_list); 204*4882a593Smuzhiyun void kfd_release_topology_device_list(struct list_head *device_list); 205*4882a593Smuzhiyun 206*4882a593Smuzhiyun #endif /* __KFD_TOPOLOGY_H__ */ 207