xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdkfd/kfd_crat.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2014 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun  * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*4882a593Smuzhiyun  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun  * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun  */
22*4882a593Smuzhiyun 
23*4882a593Smuzhiyun #ifndef KFD_CRAT_H_INCLUDED
24*4882a593Smuzhiyun #define KFD_CRAT_H_INCLUDED
25*4882a593Smuzhiyun 
26*4882a593Smuzhiyun #include <linux/types.h>
27*4882a593Smuzhiyun 
28*4882a593Smuzhiyun #pragma pack(1)
29*4882a593Smuzhiyun 
30*4882a593Smuzhiyun /*
31*4882a593Smuzhiyun  * 4CC signature values for the CRAT and CDIT ACPI tables
32*4882a593Smuzhiyun  */
33*4882a593Smuzhiyun 
34*4882a593Smuzhiyun #define CRAT_SIGNATURE	"CRAT"
35*4882a593Smuzhiyun #define CDIT_SIGNATURE	"CDIT"
36*4882a593Smuzhiyun 
37*4882a593Smuzhiyun /*
38*4882a593Smuzhiyun  * Component Resource Association Table (CRAT)
39*4882a593Smuzhiyun  */
40*4882a593Smuzhiyun 
41*4882a593Smuzhiyun #define CRAT_OEMID_LENGTH	6
42*4882a593Smuzhiyun #define CRAT_OEMTABLEID_LENGTH	8
43*4882a593Smuzhiyun #define CRAT_RESERVED_LENGTH	6
44*4882a593Smuzhiyun 
45*4882a593Smuzhiyun #define CRAT_OEMID_64BIT_MASK ((1ULL << (CRAT_OEMID_LENGTH * 8)) - 1)
46*4882a593Smuzhiyun 
47*4882a593Smuzhiyun /* Compute Unit flags */
48*4882a593Smuzhiyun #define COMPUTE_UNIT_CPU	(1 << 0)  /* Create Virtual CRAT for CPU */
49*4882a593Smuzhiyun #define COMPUTE_UNIT_GPU	(1 << 1)  /* Create Virtual CRAT for GPU */
50*4882a593Smuzhiyun 
51*4882a593Smuzhiyun struct crat_header {
52*4882a593Smuzhiyun 	uint32_t	signature;
53*4882a593Smuzhiyun 	uint32_t	length;
54*4882a593Smuzhiyun 	uint8_t		revision;
55*4882a593Smuzhiyun 	uint8_t		checksum;
56*4882a593Smuzhiyun 	uint8_t		oem_id[CRAT_OEMID_LENGTH];
57*4882a593Smuzhiyun 	uint8_t		oem_table_id[CRAT_OEMTABLEID_LENGTH];
58*4882a593Smuzhiyun 	uint32_t	oem_revision;
59*4882a593Smuzhiyun 	uint32_t	creator_id;
60*4882a593Smuzhiyun 	uint32_t	creator_revision;
61*4882a593Smuzhiyun 	uint32_t	total_entries;
62*4882a593Smuzhiyun 	uint16_t	num_domains;
63*4882a593Smuzhiyun 	uint8_t		reserved[CRAT_RESERVED_LENGTH];
64*4882a593Smuzhiyun };
65*4882a593Smuzhiyun 
66*4882a593Smuzhiyun /*
67*4882a593Smuzhiyun  * The header structure is immediately followed by total_entries of the
68*4882a593Smuzhiyun  * data definitions
69*4882a593Smuzhiyun  */
70*4882a593Smuzhiyun 
71*4882a593Smuzhiyun /*
72*4882a593Smuzhiyun  * The currently defined subtype entries in the CRAT
73*4882a593Smuzhiyun  */
74*4882a593Smuzhiyun #define CRAT_SUBTYPE_COMPUTEUNIT_AFFINITY	0
75*4882a593Smuzhiyun #define CRAT_SUBTYPE_MEMORY_AFFINITY		1
76*4882a593Smuzhiyun #define CRAT_SUBTYPE_CACHE_AFFINITY		2
77*4882a593Smuzhiyun #define CRAT_SUBTYPE_TLB_AFFINITY		3
78*4882a593Smuzhiyun #define CRAT_SUBTYPE_CCOMPUTE_AFFINITY		4
79*4882a593Smuzhiyun #define CRAT_SUBTYPE_IOLINK_AFFINITY		5
80*4882a593Smuzhiyun #define CRAT_SUBTYPE_MAX			6
81*4882a593Smuzhiyun 
82*4882a593Smuzhiyun #define CRAT_SIBLINGMAP_SIZE	32
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun /*
85*4882a593Smuzhiyun  * ComputeUnit Affinity structure and definitions
86*4882a593Smuzhiyun  */
87*4882a593Smuzhiyun #define CRAT_CU_FLAGS_ENABLED		0x00000001
88*4882a593Smuzhiyun #define CRAT_CU_FLAGS_HOT_PLUGGABLE	0x00000002
89*4882a593Smuzhiyun #define CRAT_CU_FLAGS_CPU_PRESENT	0x00000004
90*4882a593Smuzhiyun #define CRAT_CU_FLAGS_GPU_PRESENT	0x00000008
91*4882a593Smuzhiyun #define CRAT_CU_FLAGS_IOMMU_PRESENT	0x00000010
92*4882a593Smuzhiyun #define CRAT_CU_FLAGS_RESERVED		0xffffffe0
93*4882a593Smuzhiyun 
94*4882a593Smuzhiyun #define CRAT_COMPUTEUNIT_RESERVED_LENGTH 4
95*4882a593Smuzhiyun 
96*4882a593Smuzhiyun struct crat_subtype_computeunit {
97*4882a593Smuzhiyun 	uint8_t		type;
98*4882a593Smuzhiyun 	uint8_t		length;
99*4882a593Smuzhiyun 	uint16_t	reserved;
100*4882a593Smuzhiyun 	uint32_t	flags;
101*4882a593Smuzhiyun 	uint32_t	proximity_domain;
102*4882a593Smuzhiyun 	uint32_t	processor_id_low;
103*4882a593Smuzhiyun 	uint16_t	num_cpu_cores;
104*4882a593Smuzhiyun 	uint16_t	num_simd_cores;
105*4882a593Smuzhiyun 	uint16_t	max_waves_simd;
106*4882a593Smuzhiyun 	uint16_t	io_count;
107*4882a593Smuzhiyun 	uint16_t	hsa_capability;
108*4882a593Smuzhiyun 	uint16_t	lds_size_in_kb;
109*4882a593Smuzhiyun 	uint8_t		wave_front_size;
110*4882a593Smuzhiyun 	uint8_t		num_banks;
111*4882a593Smuzhiyun 	uint16_t	micro_engine_id;
112*4882a593Smuzhiyun 	uint8_t		array_count;
113*4882a593Smuzhiyun 	uint8_t		num_cu_per_array;
114*4882a593Smuzhiyun 	uint8_t		num_simd_per_cu;
115*4882a593Smuzhiyun 	uint8_t		max_slots_scatch_cu;
116*4882a593Smuzhiyun 	uint8_t		reserved2[CRAT_COMPUTEUNIT_RESERVED_LENGTH];
117*4882a593Smuzhiyun };
118*4882a593Smuzhiyun 
119*4882a593Smuzhiyun /*
120*4882a593Smuzhiyun  * HSA Memory Affinity structure and definitions
121*4882a593Smuzhiyun  */
122*4882a593Smuzhiyun #define CRAT_MEM_FLAGS_ENABLED		0x00000001
123*4882a593Smuzhiyun #define CRAT_MEM_FLAGS_HOT_PLUGGABLE	0x00000002
124*4882a593Smuzhiyun #define CRAT_MEM_FLAGS_NON_VOLATILE	0x00000004
125*4882a593Smuzhiyun #define CRAT_MEM_FLAGS_RESERVED		0xfffffff8
126*4882a593Smuzhiyun 
127*4882a593Smuzhiyun #define CRAT_MEMORY_RESERVED_LENGTH 8
128*4882a593Smuzhiyun 
129*4882a593Smuzhiyun struct crat_subtype_memory {
130*4882a593Smuzhiyun 	uint8_t		type;
131*4882a593Smuzhiyun 	uint8_t		length;
132*4882a593Smuzhiyun 	uint16_t	reserved;
133*4882a593Smuzhiyun 	uint32_t	flags;
134*4882a593Smuzhiyun 	uint32_t	proximity_domain;
135*4882a593Smuzhiyun 	uint32_t	base_addr_low;
136*4882a593Smuzhiyun 	uint32_t	base_addr_high;
137*4882a593Smuzhiyun 	uint32_t	length_low;
138*4882a593Smuzhiyun 	uint32_t	length_high;
139*4882a593Smuzhiyun 	uint32_t	width;
140*4882a593Smuzhiyun 	uint8_t		visibility_type; /* for virtual (dGPU) CRAT */
141*4882a593Smuzhiyun 	uint8_t		reserved2[CRAT_MEMORY_RESERVED_LENGTH - 1];
142*4882a593Smuzhiyun };
143*4882a593Smuzhiyun 
144*4882a593Smuzhiyun /*
145*4882a593Smuzhiyun  * HSA Cache Affinity structure and definitions
146*4882a593Smuzhiyun  */
147*4882a593Smuzhiyun #define CRAT_CACHE_FLAGS_ENABLED	0x00000001
148*4882a593Smuzhiyun #define CRAT_CACHE_FLAGS_DATA_CACHE	0x00000002
149*4882a593Smuzhiyun #define CRAT_CACHE_FLAGS_INST_CACHE	0x00000004
150*4882a593Smuzhiyun #define CRAT_CACHE_FLAGS_CPU_CACHE	0x00000008
151*4882a593Smuzhiyun #define CRAT_CACHE_FLAGS_SIMD_CACHE	0x00000010
152*4882a593Smuzhiyun #define CRAT_CACHE_FLAGS_RESERVED	0xffffffe0
153*4882a593Smuzhiyun 
154*4882a593Smuzhiyun #define CRAT_CACHE_RESERVED_LENGTH 8
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun struct crat_subtype_cache {
157*4882a593Smuzhiyun 	uint8_t		type;
158*4882a593Smuzhiyun 	uint8_t		length;
159*4882a593Smuzhiyun 	uint16_t	reserved;
160*4882a593Smuzhiyun 	uint32_t	flags;
161*4882a593Smuzhiyun 	uint32_t	processor_id_low;
162*4882a593Smuzhiyun 	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
163*4882a593Smuzhiyun 	uint32_t	cache_size;
164*4882a593Smuzhiyun 	uint8_t		cache_level;
165*4882a593Smuzhiyun 	uint8_t		lines_per_tag;
166*4882a593Smuzhiyun 	uint16_t	cache_line_size;
167*4882a593Smuzhiyun 	uint8_t		associativity;
168*4882a593Smuzhiyun 	uint8_t		cache_properties;
169*4882a593Smuzhiyun 	uint16_t	cache_latency;
170*4882a593Smuzhiyun 	uint8_t		reserved2[CRAT_CACHE_RESERVED_LENGTH];
171*4882a593Smuzhiyun };
172*4882a593Smuzhiyun 
173*4882a593Smuzhiyun /*
174*4882a593Smuzhiyun  * HSA TLB Affinity structure and definitions
175*4882a593Smuzhiyun  */
176*4882a593Smuzhiyun #define CRAT_TLB_FLAGS_ENABLED	0x00000001
177*4882a593Smuzhiyun #define CRAT_TLB_FLAGS_DATA_TLB	0x00000002
178*4882a593Smuzhiyun #define CRAT_TLB_FLAGS_INST_TLB	0x00000004
179*4882a593Smuzhiyun #define CRAT_TLB_FLAGS_CPU_TLB	0x00000008
180*4882a593Smuzhiyun #define CRAT_TLB_FLAGS_SIMD_TLB	0x00000010
181*4882a593Smuzhiyun #define CRAT_TLB_FLAGS_RESERVED	0xffffffe0
182*4882a593Smuzhiyun 
183*4882a593Smuzhiyun #define CRAT_TLB_RESERVED_LENGTH 4
184*4882a593Smuzhiyun 
185*4882a593Smuzhiyun struct crat_subtype_tlb {
186*4882a593Smuzhiyun 	uint8_t		type;
187*4882a593Smuzhiyun 	uint8_t		length;
188*4882a593Smuzhiyun 	uint16_t	reserved;
189*4882a593Smuzhiyun 	uint32_t	flags;
190*4882a593Smuzhiyun 	uint32_t	processor_id_low;
191*4882a593Smuzhiyun 	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
192*4882a593Smuzhiyun 	uint32_t	tlb_level;
193*4882a593Smuzhiyun 	uint8_t		data_tlb_associativity_2mb;
194*4882a593Smuzhiyun 	uint8_t		data_tlb_size_2mb;
195*4882a593Smuzhiyun 	uint8_t		instruction_tlb_associativity_2mb;
196*4882a593Smuzhiyun 	uint8_t		instruction_tlb_size_2mb;
197*4882a593Smuzhiyun 	uint8_t		data_tlb_associativity_4k;
198*4882a593Smuzhiyun 	uint8_t		data_tlb_size_4k;
199*4882a593Smuzhiyun 	uint8_t		instruction_tlb_associativity_4k;
200*4882a593Smuzhiyun 	uint8_t		instruction_tlb_size_4k;
201*4882a593Smuzhiyun 	uint8_t		data_tlb_associativity_1gb;
202*4882a593Smuzhiyun 	uint8_t		data_tlb_size_1gb;
203*4882a593Smuzhiyun 	uint8_t		instruction_tlb_associativity_1gb;
204*4882a593Smuzhiyun 	uint8_t		instruction_tlb_size_1gb;
205*4882a593Smuzhiyun 	uint8_t		reserved2[CRAT_TLB_RESERVED_LENGTH];
206*4882a593Smuzhiyun };
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun /*
209*4882a593Smuzhiyun  * HSA CCompute/APU Affinity structure and definitions
210*4882a593Smuzhiyun  */
211*4882a593Smuzhiyun #define CRAT_CCOMPUTE_FLAGS_ENABLED	0x00000001
212*4882a593Smuzhiyun #define CRAT_CCOMPUTE_FLAGS_RESERVED	0xfffffffe
213*4882a593Smuzhiyun 
214*4882a593Smuzhiyun #define CRAT_CCOMPUTE_RESERVED_LENGTH 16
215*4882a593Smuzhiyun 
216*4882a593Smuzhiyun struct crat_subtype_ccompute {
217*4882a593Smuzhiyun 	uint8_t		type;
218*4882a593Smuzhiyun 	uint8_t		length;
219*4882a593Smuzhiyun 	uint16_t	reserved;
220*4882a593Smuzhiyun 	uint32_t	flags;
221*4882a593Smuzhiyun 	uint32_t	processor_id_low;
222*4882a593Smuzhiyun 	uint8_t		sibling_map[CRAT_SIBLINGMAP_SIZE];
223*4882a593Smuzhiyun 	uint32_t	apu_size;
224*4882a593Smuzhiyun 	uint8_t		reserved2[CRAT_CCOMPUTE_RESERVED_LENGTH];
225*4882a593Smuzhiyun };
226*4882a593Smuzhiyun 
227*4882a593Smuzhiyun /*
228*4882a593Smuzhiyun  * HSA IO Link Affinity structure and definitions
229*4882a593Smuzhiyun  */
230*4882a593Smuzhiyun #define CRAT_IOLINK_FLAGS_ENABLED		(1 << 0)
231*4882a593Smuzhiyun #define CRAT_IOLINK_FLAGS_NON_COHERENT		(1 << 1)
232*4882a593Smuzhiyun #define CRAT_IOLINK_FLAGS_NO_ATOMICS_32_BIT	(1 << 2)
233*4882a593Smuzhiyun #define CRAT_IOLINK_FLAGS_NO_ATOMICS_64_BIT	(1 << 3)
234*4882a593Smuzhiyun #define CRAT_IOLINK_FLAGS_NO_PEER_TO_PEER_DMA	(1 << 4)
235*4882a593Smuzhiyun #define CRAT_IOLINK_FLAGS_BI_DIRECTIONAL 	(1 << 31)
236*4882a593Smuzhiyun #define CRAT_IOLINK_FLAGS_RESERVED_MASK		0x7fffffe0
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun /*
239*4882a593Smuzhiyun  * IO interface types
240*4882a593Smuzhiyun  */
241*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_UNDEFINED	0
242*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_HYPERTRANSPORT	1
243*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_PCIEXPRESS	2
244*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_AMBA		3
245*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_MIPI		4
246*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_QPI_1_1	5
247*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_RESERVED1	6
248*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_RESERVED2	7
249*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_RAPID_IO	8
250*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_INFINIBAND	9
251*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_RESERVED3	10
252*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_XGMI		11
253*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_XGOP		12
254*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_GZ		13
255*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_ETHERNET_RDMA	14
256*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_RDMA_OTHER	15
257*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_OTHER		16
258*4882a593Smuzhiyun #define CRAT_IOLINK_TYPE_MAX		255
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun #define CRAT_IOLINK_RESERVED_LENGTH	24
261*4882a593Smuzhiyun 
262*4882a593Smuzhiyun struct crat_subtype_iolink {
263*4882a593Smuzhiyun 	uint8_t		type;
264*4882a593Smuzhiyun 	uint8_t		length;
265*4882a593Smuzhiyun 	uint16_t	reserved;
266*4882a593Smuzhiyun 	uint32_t	flags;
267*4882a593Smuzhiyun 	uint32_t	proximity_domain_from;
268*4882a593Smuzhiyun 	uint32_t	proximity_domain_to;
269*4882a593Smuzhiyun 	uint8_t		io_interface_type;
270*4882a593Smuzhiyun 	uint8_t		version_major;
271*4882a593Smuzhiyun 	uint16_t	version_minor;
272*4882a593Smuzhiyun 	uint32_t	minimum_latency;
273*4882a593Smuzhiyun 	uint32_t	maximum_latency;
274*4882a593Smuzhiyun 	uint32_t	minimum_bandwidth_mbs;
275*4882a593Smuzhiyun 	uint32_t	maximum_bandwidth_mbs;
276*4882a593Smuzhiyun 	uint32_t	recommended_transfer_size;
277*4882a593Smuzhiyun 	uint8_t		reserved2[CRAT_IOLINK_RESERVED_LENGTH - 1];
278*4882a593Smuzhiyun 	uint8_t		num_hops_xgmi;
279*4882a593Smuzhiyun };
280*4882a593Smuzhiyun 
281*4882a593Smuzhiyun /*
282*4882a593Smuzhiyun  * HSA generic sub-type header
283*4882a593Smuzhiyun  */
284*4882a593Smuzhiyun 
285*4882a593Smuzhiyun #define CRAT_SUBTYPE_FLAGS_ENABLED 0x00000001
286*4882a593Smuzhiyun 
287*4882a593Smuzhiyun struct crat_subtype_generic {
288*4882a593Smuzhiyun 	uint8_t		type;
289*4882a593Smuzhiyun 	uint8_t		length;
290*4882a593Smuzhiyun 	uint16_t	reserved;
291*4882a593Smuzhiyun 	uint32_t	flags;
292*4882a593Smuzhiyun };
293*4882a593Smuzhiyun 
294*4882a593Smuzhiyun /*
295*4882a593Smuzhiyun  * Component Locality Distance Information Table (CDIT)
296*4882a593Smuzhiyun  */
297*4882a593Smuzhiyun #define CDIT_OEMID_LENGTH	6
298*4882a593Smuzhiyun #define CDIT_OEMTABLEID_LENGTH	8
299*4882a593Smuzhiyun 
300*4882a593Smuzhiyun struct cdit_header {
301*4882a593Smuzhiyun 	uint32_t	signature;
302*4882a593Smuzhiyun 	uint32_t	length;
303*4882a593Smuzhiyun 	uint8_t		revision;
304*4882a593Smuzhiyun 	uint8_t		checksum;
305*4882a593Smuzhiyun 	uint8_t		oem_id[CDIT_OEMID_LENGTH];
306*4882a593Smuzhiyun 	uint8_t		oem_table_id[CDIT_OEMTABLEID_LENGTH];
307*4882a593Smuzhiyun 	uint32_t	oem_revision;
308*4882a593Smuzhiyun 	uint32_t	creator_id;
309*4882a593Smuzhiyun 	uint32_t	creator_revision;
310*4882a593Smuzhiyun 	uint32_t	total_entries;
311*4882a593Smuzhiyun 	uint16_t	num_domains;
312*4882a593Smuzhiyun 	uint8_t		entry[1];
313*4882a593Smuzhiyun };
314*4882a593Smuzhiyun 
315*4882a593Smuzhiyun #pragma pack()
316*4882a593Smuzhiyun 
317*4882a593Smuzhiyun struct kfd_dev;
318*4882a593Smuzhiyun 
319*4882a593Smuzhiyun int kfd_create_crat_image_acpi(void **crat_image, size_t *size);
320*4882a593Smuzhiyun void kfd_destroy_crat_image(void *crat_image);
321*4882a593Smuzhiyun int kfd_parse_crat_table(void *crat_image, struct list_head *device_list,
322*4882a593Smuzhiyun 			 uint32_t proximity_domain);
323*4882a593Smuzhiyun int kfd_create_crat_image_virtual(void **crat_image, size_t *size,
324*4882a593Smuzhiyun 				  int flags, struct kfd_dev *kdev,
325*4882a593Smuzhiyun 				  uint32_t proximity_domain);
326*4882a593Smuzhiyun 
327*4882a593Smuzhiyun #endif /* KFD_CRAT_H_INCLUDED */
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