1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifndef CIK_REGS_H 24*4882a593Smuzhiyun #define CIK_REGS_H 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun /* if PTR32, these are the bases for scratch and lds */ 27*4882a593Smuzhiyun #define PRIVATE_BASE(x) ((x) << 0) /* scratch */ 28*4882a593Smuzhiyun #define SHARED_BASE(x) ((x) << 16) /* LDS */ 29*4882a593Smuzhiyun #define PTR32 (1 << 0) 30*4882a593Smuzhiyun #define ALIGNMENT_MODE(x) ((x) << 2) 31*4882a593Smuzhiyun #define SH_MEM_ALIGNMENT_MODE_UNALIGNED 3 32*4882a593Smuzhiyun #define DEFAULT_MTYPE(x) ((x) << 4) 33*4882a593Smuzhiyun #define APE1_MTYPE(x) ((x) << 7) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun /* valid for both DEFAULT_MTYPE and APE1_MTYPE */ 36*4882a593Smuzhiyun #define MTYPE_CACHED_NV 0 37*4882a593Smuzhiyun #define MTYPE_CACHED 1 38*4882a593Smuzhiyun #define MTYPE_NONCACHED 3 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define DEFAULT_CP_HQD_PERSISTENT_STATE (0x33U << 8) 41*4882a593Smuzhiyun #define PRELOAD_REQ (1 << 0) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun #define MQD_CONTROL_PRIV_STATE_EN (1U << 8) 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun #define DEFAULT_MIN_IB_AVAIL_SIZE (3U << 20) 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun #define IB_ATC_EN (1U << 23) 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun #define QUANTUM_EN 1U 50*4882a593Smuzhiyun #define QUANTUM_SCALE_1MS (1U << 4) 51*4882a593Smuzhiyun #define QUANTUM_DURATION(x) ((x) << 8) 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun #define RPTR_BLOCK_SIZE(x) ((x) << 8) 54*4882a593Smuzhiyun #define MIN_AVAIL_SIZE(x) ((x) << 20) 55*4882a593Smuzhiyun #define DEFAULT_RPTR_BLOCK_SIZE RPTR_BLOCK_SIZE(5) 56*4882a593Smuzhiyun #define DEFAULT_MIN_AVAIL_SIZE MIN_AVAIL_SIZE(3) 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #define PQ_ATC_EN (1 << 23) 59*4882a593Smuzhiyun #define NO_UPDATE_RPTR (1 << 27) 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun #define DOORBELL_OFFSET(x) ((x) << 2) 62*4882a593Smuzhiyun #define DOORBELL_EN (1 << 30) 63*4882a593Smuzhiyun 64*4882a593Smuzhiyun #define PRIV_STATE (1 << 30) 65*4882a593Smuzhiyun #define KMD_QUEUE (1 << 31) 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define AQL_ENABLE 1 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun #define GRBM_GFX_INDEX 0x30800 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun #endif 72