1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2016 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __SOC15_H__ 25*4882a593Smuzhiyun #define __SOC15_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #include "nbio_v6_1.h" 28*4882a593Smuzhiyun #include "nbio_v7_0.h" 29*4882a593Smuzhiyun #include "nbio_v7_4.h" 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define SOC15_FLUSH_GPU_TLB_NUM_WREG 6 32*4882a593Smuzhiyun #define SOC15_FLUSH_GPU_TLB_NUM_REG_WAIT 3 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun extern const struct amd_ip_funcs soc15_common_ip_funcs; 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct soc15_reg_golden { 37*4882a593Smuzhiyun u32 hwip; 38*4882a593Smuzhiyun u32 instance; 39*4882a593Smuzhiyun u32 segment; 40*4882a593Smuzhiyun u32 reg; 41*4882a593Smuzhiyun u32 and_mask; 42*4882a593Smuzhiyun u32 or_mask; 43*4882a593Smuzhiyun }; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun struct soc15_reg_rlcg { 46*4882a593Smuzhiyun u32 hwip; 47*4882a593Smuzhiyun u32 instance; 48*4882a593Smuzhiyun u32 segment; 49*4882a593Smuzhiyun u32 reg; 50*4882a593Smuzhiyun }; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct soc15_reg_entry { 53*4882a593Smuzhiyun uint32_t hwip; 54*4882a593Smuzhiyun uint32_t inst; 55*4882a593Smuzhiyun uint32_t seg; 56*4882a593Smuzhiyun uint32_t reg_offset; 57*4882a593Smuzhiyun uint32_t reg_value; 58*4882a593Smuzhiyun uint32_t se_num; 59*4882a593Smuzhiyun uint32_t instance; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun struct soc15_allowed_register_entry { 63*4882a593Smuzhiyun uint32_t hwip; 64*4882a593Smuzhiyun uint32_t inst; 65*4882a593Smuzhiyun uint32_t seg; 66*4882a593Smuzhiyun uint32_t reg_offset; 67*4882a593Smuzhiyun bool grbm_indexed; 68*4882a593Smuzhiyun }; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun struct soc15_ras_field_entry { 71*4882a593Smuzhiyun const char *name; 72*4882a593Smuzhiyun uint32_t hwip; 73*4882a593Smuzhiyun uint32_t inst; 74*4882a593Smuzhiyun uint32_t seg; 75*4882a593Smuzhiyun uint32_t reg_offset; 76*4882a593Smuzhiyun uint32_t sec_count_mask; 77*4882a593Smuzhiyun uint32_t sec_count_shift; 78*4882a593Smuzhiyun uint32_t ded_count_mask; 79*4882a593Smuzhiyun uint32_t ded_count_shift; 80*4882a593Smuzhiyun }; 81*4882a593Smuzhiyun 82*4882a593Smuzhiyun #define SOC15_REG_ENTRY(ip, inst, reg) ip##_HWIP, inst, reg##_BASE_IDX, reg 83*4882a593Smuzhiyun 84*4882a593Smuzhiyun #define SOC15_REG_ENTRY_OFFSET(entry) (adev->reg_offset[entry.hwip][entry.inst][entry.seg] + entry.reg_offset) 85*4882a593Smuzhiyun 86*4882a593Smuzhiyun #define SOC15_REG_GOLDEN_VALUE(ip, inst, reg, and_mask, or_mask) \ 87*4882a593Smuzhiyun { ip##_HWIP, inst, reg##_BASE_IDX, reg, and_mask, or_mask } 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun #define SOC15_REG_FIELD(reg, field) reg##__##field##_MASK, reg##__##field##__SHIFT 90*4882a593Smuzhiyun 91*4882a593Smuzhiyun void soc15_grbm_select(struct amdgpu_device *adev, 92*4882a593Smuzhiyun u32 me, u32 pipe, u32 queue, u32 vmid); 93*4882a593Smuzhiyun void soc15_set_virt_ops(struct amdgpu_device *adev); 94*4882a593Smuzhiyun int soc15_set_ip_blocks(struct amdgpu_device *adev); 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun void soc15_program_register_sequence(struct amdgpu_device *adev, 97*4882a593Smuzhiyun const struct soc15_reg_golden *registers, 98*4882a593Smuzhiyun const u32 array_size); 99*4882a593Smuzhiyun 100*4882a593Smuzhiyun int vega10_reg_base_init(struct amdgpu_device *adev); 101*4882a593Smuzhiyun int vega20_reg_base_init(struct amdgpu_device *adev); 102*4882a593Smuzhiyun int arct_reg_base_init(struct amdgpu_device *adev); 103*4882a593Smuzhiyun 104*4882a593Smuzhiyun void vega10_doorbell_index_init(struct amdgpu_device *adev); 105*4882a593Smuzhiyun void vega20_doorbell_index_init(struct amdgpu_device *adev); 106*4882a593Smuzhiyun #endif 107