1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2019 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __NV_H__ 25*4882a593Smuzhiyun #define __NV_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #include "nbio_v2_3.h" 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun void nv_grbm_select(struct amdgpu_device *adev, 30*4882a593Smuzhiyun u32 me, u32 pipe, u32 queue, u32 vmid); 31*4882a593Smuzhiyun void nv_set_virt_ops(struct amdgpu_device *adev); 32*4882a593Smuzhiyun int nv_set_ip_blocks(struct amdgpu_device *adev); 33*4882a593Smuzhiyun int navi10_reg_base_init(struct amdgpu_device *adev); 34*4882a593Smuzhiyun int navi14_reg_base_init(struct amdgpu_device *adev); 35*4882a593Smuzhiyun int navi12_reg_base_init(struct amdgpu_device *adev); 36*4882a593Smuzhiyun int sienna_cichlid_reg_base_init(struct amdgpu_device *adev); 37*4882a593Smuzhiyun #endif 38