1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2017 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun */ 22*4882a593Smuzhiyun 23*4882a593Smuzhiyun #ifndef __MXGPU_VI_H__ 24*4882a593Smuzhiyun #define __MXGPU_VI_H__ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #define VI_MAILBOX_TIMEDOUT 12000 27*4882a593Smuzhiyun #define VI_MAILBOX_RESET_TIME 12 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* VI mailbox messages request */ 30*4882a593Smuzhiyun enum idh_request { 31*4882a593Smuzhiyun IDH_REQ_GPU_INIT_ACCESS = 1, 32*4882a593Smuzhiyun IDH_REL_GPU_INIT_ACCESS, 33*4882a593Smuzhiyun IDH_REQ_GPU_FINI_ACCESS, 34*4882a593Smuzhiyun IDH_REL_GPU_FINI_ACCESS, 35*4882a593Smuzhiyun IDH_REQ_GPU_RESET_ACCESS, 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun IDH_LOG_VF_ERROR = 200, 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun /* VI mailbox messages data */ 41*4882a593Smuzhiyun enum idh_event { 42*4882a593Smuzhiyun IDH_CLR_MSG_BUF = 0, 43*4882a593Smuzhiyun IDH_READY_TO_ACCESS_GPU, 44*4882a593Smuzhiyun IDH_FLR_NOTIFICATION, 45*4882a593Smuzhiyun IDH_FLR_NOTIFICATION_CMPL, 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun IDH_TEXT_MESSAGE = 255 48*4882a593Smuzhiyun }; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun extern const struct amdgpu_virt_ops xgpu_vi_virt_ops; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun void xgpu_vi_init_golden_registers(struct amdgpu_device *adev); 53*4882a593Smuzhiyun void xgpu_vi_mailbox_set_irq_funcs(struct amdgpu_device *adev); 54*4882a593Smuzhiyun int xgpu_vi_mailbox_add_irq_id(struct amdgpu_device *adev); 55*4882a593Smuzhiyun int xgpu_vi_mailbox_get_irq(struct amdgpu_device *adev); 56*4882a593Smuzhiyun void xgpu_vi_mailbox_put_irq(struct amdgpu_device *adev); 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun #endif 59