1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __ATOMBIOS_CRTC_H__ 25*4882a593Smuzhiyun #define __ATOMBIOS_CRTC_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun void amdgpu_atombios_crtc_overscan_setup(struct drm_crtc *crtc, 28*4882a593Smuzhiyun struct drm_display_mode *mode, 29*4882a593Smuzhiyun struct drm_display_mode *adjusted_mode); 30*4882a593Smuzhiyun void amdgpu_atombios_crtc_scaler_setup(struct drm_crtc *crtc); 31*4882a593Smuzhiyun void amdgpu_atombios_crtc_lock(struct drm_crtc *crtc, int lock); 32*4882a593Smuzhiyun void amdgpu_atombios_crtc_enable(struct drm_crtc *crtc, int state); 33*4882a593Smuzhiyun void amdgpu_atombios_crtc_blank(struct drm_crtc *crtc, int state); 34*4882a593Smuzhiyun void amdgpu_atombios_crtc_powergate(struct drm_crtc *crtc, int state); 35*4882a593Smuzhiyun void amdgpu_atombios_crtc_powergate_init(struct amdgpu_device *adev); 36*4882a593Smuzhiyun void amdgpu_atombios_crtc_set_dtd_timing(struct drm_crtc *crtc, 37*4882a593Smuzhiyun struct drm_display_mode *mode); 38*4882a593Smuzhiyun void amdgpu_atombios_crtc_set_disp_eng_pll(struct amdgpu_device *adev, 39*4882a593Smuzhiyun u32 dispclk); 40*4882a593Smuzhiyun u32 amdgpu_atombios_crtc_set_dce_clock(struct amdgpu_device *adev, 41*4882a593Smuzhiyun u32 freq, u8 clk_type, u8 clk_src); 42*4882a593Smuzhiyun void amdgpu_atombios_crtc_program_pll(struct drm_crtc *crtc, 43*4882a593Smuzhiyun u32 crtc_id, 44*4882a593Smuzhiyun int pll_id, 45*4882a593Smuzhiyun u32 encoder_mode, 46*4882a593Smuzhiyun u32 encoder_id, 47*4882a593Smuzhiyun u32 clock, 48*4882a593Smuzhiyun u32 ref_div, 49*4882a593Smuzhiyun u32 fb_div, 50*4882a593Smuzhiyun u32 frac_fb_div, 51*4882a593Smuzhiyun u32 post_div, 52*4882a593Smuzhiyun int bpc, 53*4882a593Smuzhiyun bool ss_enabled, 54*4882a593Smuzhiyun struct amdgpu_atom_ss *ss); 55*4882a593Smuzhiyun int amdgpu_atombios_crtc_prepare_pll(struct drm_crtc *crtc, 56*4882a593Smuzhiyun struct drm_display_mode *mode); 57*4882a593Smuzhiyun void amdgpu_atombios_crtc_set_pll(struct drm_crtc *crtc, 58*4882a593Smuzhiyun struct drm_display_mode *mode); 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun #endif 61