xref: /OK3568_Linux_fs/kernel/drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h (revision 4882a59341e53eb6f0b4789bf948001014eff981)
1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun  * Copyright 2018-2019 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun  *
4*4882a593Smuzhiyun  * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun  * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun  * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun  * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun  * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun  *
11*4882a593Smuzhiyun  * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun  * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun  *
14*4882a593Smuzhiyun  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17*4882a593Smuzhiyun  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun  * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun  *
22*4882a593Smuzhiyun  */
23*4882a593Smuzhiyun 
24*4882a593Smuzhiyun #ifndef AMDGV_SRIOV_MSG__H_
25*4882a593Smuzhiyun #define AMDGV_SRIOV_MSG__H_
26*4882a593Smuzhiyun 
27*4882a593Smuzhiyun /* unit in kilobytes */
28*4882a593Smuzhiyun #define AMD_SRIOV_MSG_VBIOS_OFFSET              0
29*4882a593Smuzhiyun #define AMD_SRIOV_MSG_VBIOS_SIZE_KB             64
30*4882a593Smuzhiyun #define AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB    AMD_SRIOV_MSG_VBIOS_SIZE_KB
31*4882a593Smuzhiyun #define AMD_SRIOV_MSG_DATAEXCHANGE_SIZE_KB      4
32*4882a593Smuzhiyun 
33*4882a593Smuzhiyun /*
34*4882a593Smuzhiyun  * layout
35*4882a593Smuzhiyun  * 0           64KB        65KB        66KB
36*4882a593Smuzhiyun  * |   VBIOS   |   PF2VF   |   VF2PF   |   Bad Page   | ...
37*4882a593Smuzhiyun  * |   64KB    |   1KB     |   1KB     |
38*4882a593Smuzhiyun  */
39*4882a593Smuzhiyun #define AMD_SRIOV_MSG_SIZE_KB                   1
40*4882a593Smuzhiyun #define AMD_SRIOV_MSG_PF2VF_OFFSET_KB           AMD_SRIOV_MSG_DATAEXCHANGE_OFFSET_KB
41*4882a593Smuzhiyun #define AMD_SRIOV_MSG_VF2PF_OFFSET_KB           (AMD_SRIOV_MSG_PF2VF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
42*4882a593Smuzhiyun #define AMD_SRIOV_MSG_BAD_PAGE_OFFSET_KB        (AMD_SRIOV_MSG_VF2PF_OFFSET_KB + AMD_SRIOV_MSG_SIZE_KB)
43*4882a593Smuzhiyun 
44*4882a593Smuzhiyun /*
45*4882a593Smuzhiyun  * PF2VF history log:
46*4882a593Smuzhiyun  * v1 defined in amdgim
47*4882a593Smuzhiyun  * v2 current
48*4882a593Smuzhiyun  *
49*4882a593Smuzhiyun  * VF2PF history log:
50*4882a593Smuzhiyun  * v1 defined in amdgim
51*4882a593Smuzhiyun  * v2 defined in amdgim
52*4882a593Smuzhiyun  * v3 current
53*4882a593Smuzhiyun  */
54*4882a593Smuzhiyun #define AMD_SRIOV_MSG_FW_VRAM_PF2VF_VER			2
55*4882a593Smuzhiyun #define AMD_SRIOV_MSG_FW_VRAM_VF2PF_VER			3
56*4882a593Smuzhiyun 
57*4882a593Smuzhiyun #define AMD_SRIOV_MSG_RESERVE_UCODE		24
58*4882a593Smuzhiyun 
59*4882a593Smuzhiyun enum amd_sriov_ucode_engine_id {
60*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_VCE = 0,
61*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_UVD,
62*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_MC,
63*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_ME,
64*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_PFP,
65*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_CE,
66*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_RLC,
67*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_RLC_SRLC,
68*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_RLC_SRLG,
69*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_RLC_SRLS,
70*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_MEC,
71*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_MEC2,
72*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_SOS,
73*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_ASD,
74*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_TA_RAS,
75*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_TA_XGMI,
76*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_SMC,
77*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_SDMA,
78*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_SDMA2,
79*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_VCN,
80*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID_DMCU,
81*4882a593Smuzhiyun 	AMD_SRIOV_UCODE_ID__MAX
82*4882a593Smuzhiyun };
83*4882a593Smuzhiyun 
84*4882a593Smuzhiyun #pragma pack(push, 1) 	// PF2VF / VF2PF data areas are byte packed
85*4882a593Smuzhiyun 
86*4882a593Smuzhiyun union amd_sriov_msg_feature_flags {
87*4882a593Smuzhiyun 	struct {
88*4882a593Smuzhiyun 		uint32_t  error_log_collect  : 1;
89*4882a593Smuzhiyun 		uint32_t  host_load_ucodes   : 1;
90*4882a593Smuzhiyun 		uint32_t  host_flr_vramlost  : 1;
91*4882a593Smuzhiyun 		uint32_t  mm_bw_management   : 1;
92*4882a593Smuzhiyun 		uint32_t  pp_one_vf_mode     : 1;
93*4882a593Smuzhiyun 		uint32_t  reserved           : 27;
94*4882a593Smuzhiyun 	} flags;
95*4882a593Smuzhiyun 	uint32_t      all;
96*4882a593Smuzhiyun };
97*4882a593Smuzhiyun 
98*4882a593Smuzhiyun union amd_sriov_msg_os_info {
99*4882a593Smuzhiyun 	struct {
100*4882a593Smuzhiyun 		uint32_t  windows            : 1;
101*4882a593Smuzhiyun 		uint32_t  reserved           : 31;
102*4882a593Smuzhiyun 	} info;
103*4882a593Smuzhiyun 	uint32_t      all;
104*4882a593Smuzhiyun };
105*4882a593Smuzhiyun 
106*4882a593Smuzhiyun struct amd_sriov_msg_pf2vf_info_header {
107*4882a593Smuzhiyun 	/* the total structure size in byte */
108*4882a593Smuzhiyun 	uint32_t size;
109*4882a593Smuzhiyun 	/* version of this structure, written by the HOST */
110*4882a593Smuzhiyun 	uint32_t version;
111*4882a593Smuzhiyun 	/* reserved */
112*4882a593Smuzhiyun 	uint32_t reserved[2];
113*4882a593Smuzhiyun };
114*4882a593Smuzhiyun 
115*4882a593Smuzhiyun struct amd_sriov_msg_pf2vf_info {
116*4882a593Smuzhiyun 	/* header contains size and version */
117*4882a593Smuzhiyun 	struct amd_sriov_msg_pf2vf_info_header header;
118*4882a593Smuzhiyun 	/* use private key from mailbox 2 to create checksum */
119*4882a593Smuzhiyun 	uint32_t checksum;
120*4882a593Smuzhiyun 	/* The features flags of the HOST driver supports */
121*4882a593Smuzhiyun 	union amd_sriov_msg_feature_flags feature_flags;
122*4882a593Smuzhiyun 	/* (max_width * max_height * fps) / (16 * 16) */
123*4882a593Smuzhiyun 	uint32_t hevc_enc_max_mb_per_second;
124*4882a593Smuzhiyun 	/* (max_width * max_height) / (16 * 16) */
125*4882a593Smuzhiyun 	uint32_t hevc_enc_max_mb_per_frame;
126*4882a593Smuzhiyun 	/* (max_width * max_height * fps) / (16 * 16) */
127*4882a593Smuzhiyun 	uint32_t avc_enc_max_mb_per_second;
128*4882a593Smuzhiyun 	/* (max_width * max_height) / (16 * 16) */
129*4882a593Smuzhiyun 	uint32_t avc_enc_max_mb_per_frame;
130*4882a593Smuzhiyun 	/* MEC FW position in BYTE from the start of VF visible frame buffer */
131*4882a593Smuzhiyun 	uint64_t mecfw_offset;
132*4882a593Smuzhiyun 	/* MEC FW size in BYTE */
133*4882a593Smuzhiyun 	uint32_t mecfw_size;
134*4882a593Smuzhiyun 	/* UVD FW position in BYTE from the start of VF visible frame buffer */
135*4882a593Smuzhiyun 	uint64_t uvdfw_offset;
136*4882a593Smuzhiyun 	/* UVD FW size in BYTE */
137*4882a593Smuzhiyun 	uint32_t uvdfw_size;
138*4882a593Smuzhiyun 	/* VCE FW position in BYTE from the start of VF visible frame buffer */
139*4882a593Smuzhiyun 	uint64_t vcefw_offset;
140*4882a593Smuzhiyun 	/* VCE FW size in BYTE */
141*4882a593Smuzhiyun 	uint32_t vcefw_size;
142*4882a593Smuzhiyun 	/* Bad pages block position in BYTE */
143*4882a593Smuzhiyun 	uint32_t bp_block_offset_low;
144*4882a593Smuzhiyun 	uint32_t bp_block_offset_high;
145*4882a593Smuzhiyun 	/* Bad pages block size in BYTE */
146*4882a593Smuzhiyun 	uint32_t bp_block_size;
147*4882a593Smuzhiyun 	/* frequency for VF to update the VF2PF area in msec, 0 = manual */
148*4882a593Smuzhiyun 	uint32_t vf2pf_update_interval_ms;
149*4882a593Smuzhiyun 	/* identification in ROCm SMI */
150*4882a593Smuzhiyun 	uint64_t uuid;
151*4882a593Smuzhiyun 	uint32_t fcn_idx;
152*4882a593Smuzhiyun 	/* reserved */
153*4882a593Smuzhiyun 	uint32_t reserved[256-26];
154*4882a593Smuzhiyun };
155*4882a593Smuzhiyun 
156*4882a593Smuzhiyun struct amd_sriov_msg_vf2pf_info_header {
157*4882a593Smuzhiyun 	/* the total structure size in byte */
158*4882a593Smuzhiyun 	uint32_t size;
159*4882a593Smuzhiyun 	/* version of this structure, written by the guest */
160*4882a593Smuzhiyun 	uint32_t version;
161*4882a593Smuzhiyun 	/* reserved */
162*4882a593Smuzhiyun 	uint32_t reserved[2];
163*4882a593Smuzhiyun };
164*4882a593Smuzhiyun 
165*4882a593Smuzhiyun struct amd_sriov_msg_vf2pf_info {
166*4882a593Smuzhiyun 	/* header contains size and version */
167*4882a593Smuzhiyun 	struct amd_sriov_msg_vf2pf_info_header header;
168*4882a593Smuzhiyun 	uint32_t checksum;
169*4882a593Smuzhiyun 	/* driver version */
170*4882a593Smuzhiyun 	uint8_t  driver_version[64];
171*4882a593Smuzhiyun 	/* driver certification, 1=WHQL, 0=None */
172*4882a593Smuzhiyun 	uint32_t driver_cert;
173*4882a593Smuzhiyun 	/* guest OS type and version */
174*4882a593Smuzhiyun 	union amd_sriov_msg_os_info os_info;
175*4882a593Smuzhiyun 	/* guest fb information in the unit of MB */
176*4882a593Smuzhiyun 	uint32_t fb_usage;
177*4882a593Smuzhiyun 	/* guest gfx engine usage percentage */
178*4882a593Smuzhiyun 	uint32_t gfx_usage;
179*4882a593Smuzhiyun 	/* guest gfx engine health percentage */
180*4882a593Smuzhiyun 	uint32_t gfx_health;
181*4882a593Smuzhiyun 	/* guest compute engine usage percentage */
182*4882a593Smuzhiyun 	uint32_t compute_usage;
183*4882a593Smuzhiyun 	/* guest compute engine health percentage */
184*4882a593Smuzhiyun 	uint32_t compute_health;
185*4882a593Smuzhiyun 	/* guest avc engine usage percentage. 0xffff means N/A */
186*4882a593Smuzhiyun 	uint32_t avc_enc_usage;
187*4882a593Smuzhiyun 	/* guest avc engine health percentage. 0xffff means N/A */
188*4882a593Smuzhiyun 	uint32_t avc_enc_health;
189*4882a593Smuzhiyun 	/* guest hevc engine usage percentage. 0xffff means N/A */
190*4882a593Smuzhiyun 	uint32_t hevc_enc_usage;
191*4882a593Smuzhiyun 	/* guest hevc engine usage percentage. 0xffff means N/A */
192*4882a593Smuzhiyun 	uint32_t hevc_enc_health;
193*4882a593Smuzhiyun 	/* combined encode/decode usage */
194*4882a593Smuzhiyun 	uint32_t encode_usage;
195*4882a593Smuzhiyun 	uint32_t decode_usage;
196*4882a593Smuzhiyun 	/* Version of PF2VF that VF understands */
197*4882a593Smuzhiyun 	uint32_t pf2vf_version_required;
198*4882a593Smuzhiyun 	/* additional FB usage */
199*4882a593Smuzhiyun 	uint32_t fb_vis_usage;
200*4882a593Smuzhiyun 	uint32_t fb_vis_size;
201*4882a593Smuzhiyun 	uint32_t fb_size;
202*4882a593Smuzhiyun 	/* guest ucode data, each one is 1.25 Dword */
203*4882a593Smuzhiyun 	struct {
204*4882a593Smuzhiyun 		uint8_t  id;
205*4882a593Smuzhiyun 		uint32_t version;
206*4882a593Smuzhiyun 	} ucode_info[AMD_SRIOV_MSG_RESERVE_UCODE];
207*4882a593Smuzhiyun 
208*4882a593Smuzhiyun 	/* reserved */
209*4882a593Smuzhiyun 	uint32_t reserved[256-68];
210*4882a593Smuzhiyun };
211*4882a593Smuzhiyun 
212*4882a593Smuzhiyun /* mailbox message send from guest to host  */
213*4882a593Smuzhiyun enum amd_sriov_mailbox_request_message {
214*4882a593Smuzhiyun 	MB_REQ_MSG_REQ_GPU_INIT_ACCESS = 1,
215*4882a593Smuzhiyun 	MB_REQ_MSG_REL_GPU_INIT_ACCESS,
216*4882a593Smuzhiyun 	MB_REQ_MSG_REQ_GPU_FINI_ACCESS,
217*4882a593Smuzhiyun 	MB_REQ_MSG_REL_GPU_FINI_ACCESS,
218*4882a593Smuzhiyun 	MB_REQ_MSG_REQ_GPU_RESET_ACCESS,
219*4882a593Smuzhiyun 	MB_REQ_MSG_REQ_GPU_INIT_DATA,
220*4882a593Smuzhiyun 
221*4882a593Smuzhiyun 	MB_REQ_MSG_LOG_VF_ERROR       = 200,
222*4882a593Smuzhiyun };
223*4882a593Smuzhiyun 
224*4882a593Smuzhiyun /* mailbox message send from host to guest  */
225*4882a593Smuzhiyun enum amd_sriov_mailbox_response_message {
226*4882a593Smuzhiyun 	MB_RES_MSG_CLR_MSG_BUF = 0,
227*4882a593Smuzhiyun 	MB_RES_MSG_READY_TO_ACCESS_GPU = 1,
228*4882a593Smuzhiyun 	MB_RES_MSG_FLR_NOTIFICATION,
229*4882a593Smuzhiyun 	MB_RES_MSG_FLR_NOTIFICATION_COMPLETION,
230*4882a593Smuzhiyun 	MB_RES_MSG_SUCCESS,
231*4882a593Smuzhiyun 	MB_RES_MSG_FAIL,
232*4882a593Smuzhiyun 	MB_RES_MSG_QUERY_ALIVE,
233*4882a593Smuzhiyun 	MB_RES_MSG_GPU_INIT_DATA_READY,
234*4882a593Smuzhiyun 
235*4882a593Smuzhiyun 	MB_RES_MSG_TEXT_MESSAGE = 255
236*4882a593Smuzhiyun };
237*4882a593Smuzhiyun 
238*4882a593Smuzhiyun /* version data stored in MAILBOX_MSGBUF_RCV_DW1 for future expansion */
239*4882a593Smuzhiyun enum amd_sriov_gpu_init_data_version {
240*4882a593Smuzhiyun 	GPU_INIT_DATA_READY_V1 = 1,
241*4882a593Smuzhiyun };
242*4882a593Smuzhiyun 
243*4882a593Smuzhiyun #pragma pack(pop)	// Restore previous packing option
244*4882a593Smuzhiyun 
245*4882a593Smuzhiyun /* checksum function between host and guest */
246*4882a593Smuzhiyun unsigned int amd_sriov_msg_checksum(void *obj,
247*4882a593Smuzhiyun 				unsigned long obj_size,
248*4882a593Smuzhiyun 				unsigned int key,
249*4882a593Smuzhiyun 				unsigned int checksum);
250*4882a593Smuzhiyun 
251*4882a593Smuzhiyun /* assertion at compile time */
252*4882a593Smuzhiyun #ifdef __linux__
253*4882a593Smuzhiyun #define stringification(s) _stringification(s)
254*4882a593Smuzhiyun #define _stringification(s) #s
255*4882a593Smuzhiyun 
256*4882a593Smuzhiyun _Static_assert(
257*4882a593Smuzhiyun 	sizeof(struct amd_sriov_msg_vf2pf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
258*4882a593Smuzhiyun 	"amd_sriov_msg_vf2pf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
259*4882a593Smuzhiyun 
260*4882a593Smuzhiyun _Static_assert(
261*4882a593Smuzhiyun 	sizeof(struct amd_sriov_msg_pf2vf_info) == AMD_SRIOV_MSG_SIZE_KB << 10,
262*4882a593Smuzhiyun 	"amd_sriov_msg_pf2vf_info must be " stringification(AMD_SRIOV_MSG_SIZE_KB) " KB");
263*4882a593Smuzhiyun 
264*4882a593Smuzhiyun _Static_assert(
265*4882a593Smuzhiyun 	AMD_SRIOV_MSG_RESERVE_UCODE % 4 == 0,
266*4882a593Smuzhiyun 	"AMD_SRIOV_MSG_RESERVE_UCODE must be multiple of 4");
267*4882a593Smuzhiyun 
268*4882a593Smuzhiyun _Static_assert(
269*4882a593Smuzhiyun 	AMD_SRIOV_MSG_RESERVE_UCODE > AMD_SRIOV_UCODE_ID__MAX,
270*4882a593Smuzhiyun 	"AMD_SRIOV_MSG_RESERVE_UCODE must be bigger than AMD_SRIOV_UCODE_ID__MAX");
271*4882a593Smuzhiyun 
272*4882a593Smuzhiyun #undef _stringification
273*4882a593Smuzhiyun #undef stringification
274*4882a593Smuzhiyun #endif
275*4882a593Smuzhiyun 
276*4882a593Smuzhiyun #endif /* AMDGV_SRIOV_MSG__H_ */
277