1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2016 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun */
22*4882a593Smuzhiyun #ifndef __AMDGPU_XGMI_H__
23*4882a593Smuzhiyun #define __AMDGPU_XGMI_H__
24*4882a593Smuzhiyun
25*4882a593Smuzhiyun #include <drm/task_barrier.h>
26*4882a593Smuzhiyun #include "amdgpu_psp.h"
27*4882a593Smuzhiyun
28*4882a593Smuzhiyun
29*4882a593Smuzhiyun struct amdgpu_hive_info {
30*4882a593Smuzhiyun struct kobject kobj;
31*4882a593Smuzhiyun uint64_t hive_id;
32*4882a593Smuzhiyun struct list_head device_list;
33*4882a593Smuzhiyun struct list_head node;
34*4882a593Smuzhiyun atomic_t number_devices;
35*4882a593Smuzhiyun struct mutex hive_lock;
36*4882a593Smuzhiyun atomic_t in_reset;
37*4882a593Smuzhiyun int hi_req_count;
38*4882a593Smuzhiyun struct amdgpu_device *hi_req_gpu;
39*4882a593Smuzhiyun struct task_barrier tb;
40*4882a593Smuzhiyun enum {
41*4882a593Smuzhiyun AMDGPU_XGMI_PSTATE_MIN,
42*4882a593Smuzhiyun AMDGPU_XGMI_PSTATE_MAX_VEGA20,
43*4882a593Smuzhiyun AMDGPU_XGMI_PSTATE_UNKNOWN
44*4882a593Smuzhiyun } pstate;
45*4882a593Smuzhiyun };
46*4882a593Smuzhiyun
47*4882a593Smuzhiyun struct amdgpu_pcs_ras_field {
48*4882a593Smuzhiyun const char *err_name;
49*4882a593Smuzhiyun uint32_t pcs_err_mask;
50*4882a593Smuzhiyun uint32_t pcs_err_shift;
51*4882a593Smuzhiyun };
52*4882a593Smuzhiyun
53*4882a593Smuzhiyun struct amdgpu_hive_info *amdgpu_get_xgmi_hive(struct amdgpu_device *adev);
54*4882a593Smuzhiyun void amdgpu_put_xgmi_hive(struct amdgpu_hive_info *hive);
55*4882a593Smuzhiyun int amdgpu_xgmi_update_topology(struct amdgpu_hive_info *hive, struct amdgpu_device *adev);
56*4882a593Smuzhiyun int amdgpu_xgmi_add_device(struct amdgpu_device *adev);
57*4882a593Smuzhiyun int amdgpu_xgmi_remove_device(struct amdgpu_device *adev);
58*4882a593Smuzhiyun int amdgpu_xgmi_set_pstate(struct amdgpu_device *adev, int pstate);
59*4882a593Smuzhiyun int amdgpu_xgmi_get_hops_count(struct amdgpu_device *adev,
60*4882a593Smuzhiyun struct amdgpu_device *peer_adev);
61*4882a593Smuzhiyun int amdgpu_xgmi_ras_late_init(struct amdgpu_device *adev);
62*4882a593Smuzhiyun void amdgpu_xgmi_ras_fini(struct amdgpu_device *adev);
63*4882a593Smuzhiyun uint64_t amdgpu_xgmi_get_relative_phy_addr(struct amdgpu_device *adev,
64*4882a593Smuzhiyun uint64_t addr);
65*4882a593Smuzhiyun int amdgpu_xgmi_query_ras_error_count(struct amdgpu_device *adev,
66*4882a593Smuzhiyun void *ras_error_status);
67*4882a593Smuzhiyun void amdgpu_xgmi_reset_ras_error_count(struct amdgpu_device *adev);
68*4882a593Smuzhiyun
amdgpu_xgmi_same_hive(struct amdgpu_device * adev,struct amdgpu_device * bo_adev)69*4882a593Smuzhiyun static inline bool amdgpu_xgmi_same_hive(struct amdgpu_device *adev,
70*4882a593Smuzhiyun struct amdgpu_device *bo_adev)
71*4882a593Smuzhiyun {
72*4882a593Smuzhiyun return (adev != bo_adev &&
73*4882a593Smuzhiyun adev->gmc.xgmi.hive_id &&
74*4882a593Smuzhiyun adev->gmc.xgmi.hive_id == bo_adev->gmc.xgmi.hive_id);
75*4882a593Smuzhiyun }
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun #endif
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