1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __AMDGPU_VCE_H__ 25*4882a593Smuzhiyun #define __AMDGPU_VCE_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define AMDGPU_MAX_VCE_HANDLES 16 28*4882a593Smuzhiyun #define AMDGPU_VCE_FIRMWARE_OFFSET 256 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun #define AMDGPU_VCE_HARVEST_VCE0 (1 << 0) 31*4882a593Smuzhiyun #define AMDGPU_VCE_HARVEST_VCE1 (1 << 1) 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun #define AMDGPU_VCE_FW_53_45 ((53 << 24) | (45 << 16)) 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun struct amdgpu_vce { 36*4882a593Smuzhiyun struct amdgpu_bo *vcpu_bo; 37*4882a593Smuzhiyun uint64_t gpu_addr; 38*4882a593Smuzhiyun void *cpu_addr; 39*4882a593Smuzhiyun void *saved_bo; 40*4882a593Smuzhiyun unsigned fw_version; 41*4882a593Smuzhiyun unsigned fb_version; 42*4882a593Smuzhiyun atomic_t handles[AMDGPU_MAX_VCE_HANDLES]; 43*4882a593Smuzhiyun struct drm_file *filp[AMDGPU_MAX_VCE_HANDLES]; 44*4882a593Smuzhiyun uint32_t img_size[AMDGPU_MAX_VCE_HANDLES]; 45*4882a593Smuzhiyun struct delayed_work idle_work; 46*4882a593Smuzhiyun struct mutex idle_mutex; 47*4882a593Smuzhiyun const struct firmware *fw; /* VCE firmware */ 48*4882a593Smuzhiyun struct amdgpu_ring ring[AMDGPU_MAX_VCE_RINGS]; 49*4882a593Smuzhiyun struct amdgpu_irq_src irq; 50*4882a593Smuzhiyun unsigned harvest_config; 51*4882a593Smuzhiyun struct drm_sched_entity entity; 52*4882a593Smuzhiyun uint32_t srbm_soft_reset; 53*4882a593Smuzhiyun unsigned num_rings; 54*4882a593Smuzhiyun }; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun int amdgpu_vce_sw_init(struct amdgpu_device *adev, unsigned long size); 57*4882a593Smuzhiyun int amdgpu_vce_sw_fini(struct amdgpu_device *adev); 58*4882a593Smuzhiyun int amdgpu_vce_entity_init(struct amdgpu_device *adev); 59*4882a593Smuzhiyun int amdgpu_vce_suspend(struct amdgpu_device *adev); 60*4882a593Smuzhiyun int amdgpu_vce_resume(struct amdgpu_device *adev); 61*4882a593Smuzhiyun void amdgpu_vce_free_handles(struct amdgpu_device *adev, struct drm_file *filp); 62*4882a593Smuzhiyun int amdgpu_vce_ring_parse_cs(struct amdgpu_cs_parser *p, uint32_t ib_idx); 63*4882a593Smuzhiyun int amdgpu_vce_ring_parse_cs_vm(struct amdgpu_cs_parser *p, uint32_t ib_idx); 64*4882a593Smuzhiyun void amdgpu_vce_ring_emit_ib(struct amdgpu_ring *ring, struct amdgpu_job *job, 65*4882a593Smuzhiyun struct amdgpu_ib *ib, uint32_t flags); 66*4882a593Smuzhiyun void amdgpu_vce_ring_emit_fence(struct amdgpu_ring *ring, u64 addr, u64 seq, 67*4882a593Smuzhiyun unsigned flags); 68*4882a593Smuzhiyun int amdgpu_vce_ring_test_ring(struct amdgpu_ring *ring); 69*4882a593Smuzhiyun int amdgpu_vce_ring_test_ib(struct amdgpu_ring *ring, long timeout); 70*4882a593Smuzhiyun void amdgpu_vce_ring_begin_use(struct amdgpu_ring *ring); 71*4882a593Smuzhiyun void amdgpu_vce_ring_end_use(struct amdgpu_ring *ring); 72*4882a593Smuzhiyun unsigned amdgpu_vce_ring_get_emit_ib_size(struct amdgpu_ring *ring); 73*4882a593Smuzhiyun unsigned amdgpu_vce_ring_get_dma_frame_size(struct amdgpu_ring *ring); 74*4882a593Smuzhiyun 75*4882a593Smuzhiyun #endif 76