1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2019 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included 12*4882a593Smuzhiyun * in all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15*4882a593Smuzhiyun * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18*4882a593Smuzhiyun * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #ifndef __AMDGPU_UMC_H__ 22*4882a593Smuzhiyun #define __AMDGPU_UMC_H__ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun /* 25*4882a593Smuzhiyun * (addr / 256) * 4096, the higher 26 bits in ErrorAddr 26*4882a593Smuzhiyun * is the index of 4KB block 27*4882a593Smuzhiyun */ 28*4882a593Smuzhiyun #define ADDR_OF_4KB_BLOCK(addr) (((addr) & ~0xffULL) << 4) 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * (addr / 256) * 8192, the higher 26 bits in ErrorAddr 31*4882a593Smuzhiyun * is the index of 8KB block 32*4882a593Smuzhiyun */ 33*4882a593Smuzhiyun #define ADDR_OF_8KB_BLOCK(addr) (((addr) & ~0xffULL) << 5) 34*4882a593Smuzhiyun /* channel index is the index of 256B block */ 35*4882a593Smuzhiyun #define ADDR_OF_256B_BLOCK(channel_index) ((channel_index) << 8) 36*4882a593Smuzhiyun /* offset in 256B block */ 37*4882a593Smuzhiyun #define OFFSET_IN_256B_BLOCK(addr) ((addr) & 0xffULL) 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun #define LOOP_UMC_INST(umc_inst) for ((umc_inst) = 0; (umc_inst) < adev->umc.umc_inst_num; (umc_inst)++) 40*4882a593Smuzhiyun #define LOOP_UMC_CH_INST(ch_inst) for ((ch_inst) = 0; (ch_inst) < adev->umc.channel_inst_num; (ch_inst)++) 41*4882a593Smuzhiyun #define LOOP_UMC_INST_AND_CH(umc_inst, ch_inst) LOOP_UMC_INST((umc_inst)) LOOP_UMC_CH_INST((ch_inst)) 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct amdgpu_umc_funcs { 44*4882a593Smuzhiyun void (*err_cnt_init)(struct amdgpu_device *adev); 45*4882a593Smuzhiyun int (*ras_late_init)(struct amdgpu_device *adev); 46*4882a593Smuzhiyun void (*query_ras_error_count)(struct amdgpu_device *adev, 47*4882a593Smuzhiyun void *ras_error_status); 48*4882a593Smuzhiyun void (*query_ras_error_address)(struct amdgpu_device *adev, 49*4882a593Smuzhiyun void *ras_error_status); 50*4882a593Smuzhiyun void (*init_registers)(struct amdgpu_device *adev); 51*4882a593Smuzhiyun }; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun struct amdgpu_umc { 54*4882a593Smuzhiyun /* max error count in one ras query call */ 55*4882a593Smuzhiyun uint32_t max_ras_err_cnt_per_query; 56*4882a593Smuzhiyun /* number of umc channel instance with memory map register access */ 57*4882a593Smuzhiyun uint32_t channel_inst_num; 58*4882a593Smuzhiyun /* number of umc instance with memory map register access */ 59*4882a593Smuzhiyun uint32_t umc_inst_num; 60*4882a593Smuzhiyun /* UMC regiser per channel offset */ 61*4882a593Smuzhiyun uint32_t channel_offs; 62*4882a593Smuzhiyun /* channel index table of interleaved memory */ 63*4882a593Smuzhiyun const uint32_t *channel_idx_tbl; 64*4882a593Smuzhiyun struct ras_common_if *ras_if; 65*4882a593Smuzhiyun 66*4882a593Smuzhiyun const struct amdgpu_umc_funcs *funcs; 67*4882a593Smuzhiyun }; 68*4882a593Smuzhiyun 69*4882a593Smuzhiyun int amdgpu_umc_ras_late_init(struct amdgpu_device *adev); 70*4882a593Smuzhiyun void amdgpu_umc_ras_fini(struct amdgpu_device *adev); 71*4882a593Smuzhiyun int amdgpu_umc_process_ras_data_cb(struct amdgpu_device *adev, 72*4882a593Smuzhiyun void *ras_error_status, 73*4882a593Smuzhiyun struct amdgpu_iv_entry *entry); 74*4882a593Smuzhiyun int amdgpu_umc_process_ecc_irq(struct amdgpu_device *adev, 75*4882a593Smuzhiyun struct amdgpu_irq_src *source, 76*4882a593Smuzhiyun struct amdgpu_iv_entry *entry); 77*4882a593Smuzhiyun #endif 78