1*4882a593Smuzhiyun /*
2*4882a593Smuzhiyun * Copyright 2016 Advanced Micro Devices, Inc.
3*4882a593Smuzhiyun *
4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a
5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"),
6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation
7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the
9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions:
10*4882a593Smuzhiyun *
11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in
12*4882a593Smuzhiyun * all copies or substantial portions of the Software.
13*4882a593Smuzhiyun *
14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE.
21*4882a593Smuzhiyun *
22*4882a593Smuzhiyun */
23*4882a593Smuzhiyun
24*4882a593Smuzhiyun #ifndef __AMDGPU_TTM_H__
25*4882a593Smuzhiyun #define __AMDGPU_TTM_H__
26*4882a593Smuzhiyun
27*4882a593Smuzhiyun #include <linux/dma-direction.h>
28*4882a593Smuzhiyun #include <drm/gpu_scheduler.h>
29*4882a593Smuzhiyun #include "amdgpu.h"
30*4882a593Smuzhiyun
31*4882a593Smuzhiyun #define AMDGPU_PL_GDS (TTM_PL_PRIV + 0)
32*4882a593Smuzhiyun #define AMDGPU_PL_GWS (TTM_PL_PRIV + 1)
33*4882a593Smuzhiyun #define AMDGPU_PL_OA (TTM_PL_PRIV + 2)
34*4882a593Smuzhiyun
35*4882a593Smuzhiyun #define AMDGPU_GTT_MAX_TRANSFER_SIZE 512
36*4882a593Smuzhiyun #define AMDGPU_GTT_NUM_TRANSFER_WINDOWS 2
37*4882a593Smuzhiyun
38*4882a593Smuzhiyun #define AMDGPU_POISON 0xd0bed0be
39*4882a593Smuzhiyun
40*4882a593Smuzhiyun struct amdgpu_vram_mgr {
41*4882a593Smuzhiyun struct ttm_resource_manager manager;
42*4882a593Smuzhiyun struct drm_mm mm;
43*4882a593Smuzhiyun spinlock_t lock;
44*4882a593Smuzhiyun atomic64_t usage;
45*4882a593Smuzhiyun atomic64_t vis_usage;
46*4882a593Smuzhiyun };
47*4882a593Smuzhiyun
48*4882a593Smuzhiyun struct amdgpu_gtt_mgr {
49*4882a593Smuzhiyun struct ttm_resource_manager manager;
50*4882a593Smuzhiyun struct drm_mm mm;
51*4882a593Smuzhiyun spinlock_t lock;
52*4882a593Smuzhiyun atomic64_t available;
53*4882a593Smuzhiyun };
54*4882a593Smuzhiyun
55*4882a593Smuzhiyun struct amdgpu_mman {
56*4882a593Smuzhiyun struct ttm_bo_device bdev;
57*4882a593Smuzhiyun bool mem_global_referenced;
58*4882a593Smuzhiyun bool initialized;
59*4882a593Smuzhiyun void __iomem *aper_base_kaddr;
60*4882a593Smuzhiyun
61*4882a593Smuzhiyun #if defined(CONFIG_DEBUG_FS)
62*4882a593Smuzhiyun struct dentry *debugfs_entries[8];
63*4882a593Smuzhiyun #endif
64*4882a593Smuzhiyun
65*4882a593Smuzhiyun /* buffer handling */
66*4882a593Smuzhiyun const struct amdgpu_buffer_funcs *buffer_funcs;
67*4882a593Smuzhiyun struct amdgpu_ring *buffer_funcs_ring;
68*4882a593Smuzhiyun bool buffer_funcs_enabled;
69*4882a593Smuzhiyun
70*4882a593Smuzhiyun struct mutex gtt_window_lock;
71*4882a593Smuzhiyun /* Scheduler entity for buffer moves */
72*4882a593Smuzhiyun struct drm_sched_entity entity;
73*4882a593Smuzhiyun
74*4882a593Smuzhiyun struct amdgpu_vram_mgr vram_mgr;
75*4882a593Smuzhiyun struct amdgpu_gtt_mgr gtt_mgr;
76*4882a593Smuzhiyun
77*4882a593Smuzhiyun uint64_t stolen_vga_size;
78*4882a593Smuzhiyun struct amdgpu_bo *stolen_vga_memory;
79*4882a593Smuzhiyun uint64_t stolen_extended_size;
80*4882a593Smuzhiyun struct amdgpu_bo *stolen_extended_memory;
81*4882a593Smuzhiyun bool keep_stolen_vga_memory;
82*4882a593Smuzhiyun
83*4882a593Smuzhiyun /* discovery */
84*4882a593Smuzhiyun uint8_t *discovery_bin;
85*4882a593Smuzhiyun uint32_t discovery_tmr_size;
86*4882a593Smuzhiyun struct amdgpu_bo *discovery_memory;
87*4882a593Smuzhiyun
88*4882a593Smuzhiyun /* firmware VRAM reservation */
89*4882a593Smuzhiyun u64 fw_vram_usage_start_offset;
90*4882a593Smuzhiyun u64 fw_vram_usage_size;
91*4882a593Smuzhiyun struct amdgpu_bo *fw_vram_usage_reserved_bo;
92*4882a593Smuzhiyun void *fw_vram_usage_va;
93*4882a593Smuzhiyun };
94*4882a593Smuzhiyun
95*4882a593Smuzhiyun struct amdgpu_copy_mem {
96*4882a593Smuzhiyun struct ttm_buffer_object *bo;
97*4882a593Smuzhiyun struct ttm_resource *mem;
98*4882a593Smuzhiyun unsigned long offset;
99*4882a593Smuzhiyun };
100*4882a593Smuzhiyun
101*4882a593Smuzhiyun int amdgpu_gtt_mgr_init(struct amdgpu_device *adev, uint64_t gtt_size);
102*4882a593Smuzhiyun void amdgpu_gtt_mgr_fini(struct amdgpu_device *adev);
103*4882a593Smuzhiyun int amdgpu_vram_mgr_init(struct amdgpu_device *adev);
104*4882a593Smuzhiyun void amdgpu_vram_mgr_fini(struct amdgpu_device *adev);
105*4882a593Smuzhiyun
106*4882a593Smuzhiyun bool amdgpu_gtt_mgr_has_gart_addr(struct ttm_resource *mem);
107*4882a593Smuzhiyun uint64_t amdgpu_gtt_mgr_usage(struct ttm_resource_manager *man);
108*4882a593Smuzhiyun int amdgpu_gtt_mgr_recover(struct ttm_resource_manager *man);
109*4882a593Smuzhiyun
110*4882a593Smuzhiyun u64 amdgpu_vram_mgr_bo_visible_size(struct amdgpu_bo *bo);
111*4882a593Smuzhiyun int amdgpu_vram_mgr_alloc_sgt(struct amdgpu_device *adev,
112*4882a593Smuzhiyun struct ttm_resource *mem,
113*4882a593Smuzhiyun struct device *dev,
114*4882a593Smuzhiyun enum dma_data_direction dir,
115*4882a593Smuzhiyun struct sg_table **sgt);
116*4882a593Smuzhiyun void amdgpu_vram_mgr_free_sgt(struct amdgpu_device *adev,
117*4882a593Smuzhiyun struct device *dev,
118*4882a593Smuzhiyun enum dma_data_direction dir,
119*4882a593Smuzhiyun struct sg_table *sgt);
120*4882a593Smuzhiyun uint64_t amdgpu_vram_mgr_usage(struct ttm_resource_manager *man);
121*4882a593Smuzhiyun uint64_t amdgpu_vram_mgr_vis_usage(struct ttm_resource_manager *man);
122*4882a593Smuzhiyun
123*4882a593Smuzhiyun int amdgpu_ttm_init(struct amdgpu_device *adev);
124*4882a593Smuzhiyun void amdgpu_ttm_late_init(struct amdgpu_device *adev);
125*4882a593Smuzhiyun void amdgpu_ttm_fini(struct amdgpu_device *adev);
126*4882a593Smuzhiyun void amdgpu_ttm_set_buffer_funcs_status(struct amdgpu_device *adev,
127*4882a593Smuzhiyun bool enable);
128*4882a593Smuzhiyun
129*4882a593Smuzhiyun int amdgpu_copy_buffer(struct amdgpu_ring *ring, uint64_t src_offset,
130*4882a593Smuzhiyun uint64_t dst_offset, uint32_t byte_count,
131*4882a593Smuzhiyun struct dma_resv *resv,
132*4882a593Smuzhiyun struct dma_fence **fence, bool direct_submit,
133*4882a593Smuzhiyun bool vm_needs_flush, bool tmz);
134*4882a593Smuzhiyun int amdgpu_ttm_copy_mem_to_mem(struct amdgpu_device *adev,
135*4882a593Smuzhiyun const struct amdgpu_copy_mem *src,
136*4882a593Smuzhiyun const struct amdgpu_copy_mem *dst,
137*4882a593Smuzhiyun uint64_t size, bool tmz,
138*4882a593Smuzhiyun struct dma_resv *resv,
139*4882a593Smuzhiyun struct dma_fence **f);
140*4882a593Smuzhiyun int amdgpu_fill_buffer(struct amdgpu_bo *bo,
141*4882a593Smuzhiyun uint32_t src_data,
142*4882a593Smuzhiyun struct dma_resv *resv,
143*4882a593Smuzhiyun struct dma_fence **fence);
144*4882a593Smuzhiyun
145*4882a593Smuzhiyun int amdgpu_mmap(struct file *filp, struct vm_area_struct *vma);
146*4882a593Smuzhiyun int amdgpu_ttm_alloc_gart(struct ttm_buffer_object *bo);
147*4882a593Smuzhiyun int amdgpu_ttm_recover_gart(struct ttm_buffer_object *tbo);
148*4882a593Smuzhiyun uint64_t amdgpu_ttm_domain_start(struct amdgpu_device *adev, uint32_t type);
149*4882a593Smuzhiyun
150*4882a593Smuzhiyun #if IS_ENABLED(CONFIG_DRM_AMDGPU_USERPTR)
151*4882a593Smuzhiyun int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo, struct page **pages);
152*4882a593Smuzhiyun bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm);
153*4882a593Smuzhiyun #else
amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo * bo,struct page ** pages)154*4882a593Smuzhiyun static inline int amdgpu_ttm_tt_get_user_pages(struct amdgpu_bo *bo,
155*4882a593Smuzhiyun struct page **pages)
156*4882a593Smuzhiyun {
157*4882a593Smuzhiyun return -EPERM;
158*4882a593Smuzhiyun }
amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt * ttm)159*4882a593Smuzhiyun static inline bool amdgpu_ttm_tt_get_user_pages_done(struct ttm_tt *ttm)
160*4882a593Smuzhiyun {
161*4882a593Smuzhiyun return false;
162*4882a593Smuzhiyun }
163*4882a593Smuzhiyun #endif
164*4882a593Smuzhiyun
165*4882a593Smuzhiyun void amdgpu_ttm_tt_set_user_pages(struct ttm_tt *ttm, struct page **pages);
166*4882a593Smuzhiyun int amdgpu_ttm_tt_set_userptr(struct ttm_buffer_object *bo,
167*4882a593Smuzhiyun uint64_t addr, uint32_t flags);
168*4882a593Smuzhiyun bool amdgpu_ttm_tt_has_userptr(struct ttm_tt *ttm);
169*4882a593Smuzhiyun struct mm_struct *amdgpu_ttm_tt_get_usermm(struct ttm_tt *ttm);
170*4882a593Smuzhiyun bool amdgpu_ttm_tt_affect_userptr(struct ttm_tt *ttm, unsigned long start,
171*4882a593Smuzhiyun unsigned long end);
172*4882a593Smuzhiyun bool amdgpu_ttm_tt_userptr_invalidated(struct ttm_tt *ttm,
173*4882a593Smuzhiyun int *last_invalidated);
174*4882a593Smuzhiyun bool amdgpu_ttm_tt_is_userptr(struct ttm_tt *ttm);
175*4882a593Smuzhiyun bool amdgpu_ttm_tt_is_readonly(struct ttm_tt *ttm);
176*4882a593Smuzhiyun uint64_t amdgpu_ttm_tt_pde_flags(struct ttm_tt *ttm, struct ttm_resource *mem);
177*4882a593Smuzhiyun uint64_t amdgpu_ttm_tt_pte_flags(struct amdgpu_device *adev, struct ttm_tt *ttm,
178*4882a593Smuzhiyun struct ttm_resource *mem);
179*4882a593Smuzhiyun
180*4882a593Smuzhiyun int amdgpu_ttm_debugfs_init(struct amdgpu_device *adev);
181*4882a593Smuzhiyun
182*4882a593Smuzhiyun #endif
183