1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright (C) 2019 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included 12*4882a593Smuzhiyun * in all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 15*4882a593Smuzhiyun * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 18*4882a593Smuzhiyun * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 19*4882a593Smuzhiyun * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 20*4882a593Smuzhiyun */ 21*4882a593Smuzhiyun #ifndef __AMDGPU_MMHUB_H__ 22*4882a593Smuzhiyun #define __AMDGPU_MMHUB_H__ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun struct amdgpu_mmhub_funcs { 25*4882a593Smuzhiyun void (*ras_init)(struct amdgpu_device *adev); 26*4882a593Smuzhiyun int (*ras_late_init)(struct amdgpu_device *adev); 27*4882a593Smuzhiyun void (*query_ras_error_count)(struct amdgpu_device *adev, 28*4882a593Smuzhiyun void *ras_error_status); 29*4882a593Smuzhiyun void (*reset_ras_error_count)(struct amdgpu_device *adev); 30*4882a593Smuzhiyun u64 (*get_fb_location)(struct amdgpu_device *adev); 31*4882a593Smuzhiyun void (*init)(struct amdgpu_device *adev); 32*4882a593Smuzhiyun int (*gart_enable)(struct amdgpu_device *adev); 33*4882a593Smuzhiyun void (*set_fault_enable_default)(struct amdgpu_device *adev, 34*4882a593Smuzhiyun bool value); 35*4882a593Smuzhiyun void (*gart_disable)(struct amdgpu_device *adev); 36*4882a593Smuzhiyun int (*set_clockgating)(struct amdgpu_device *adev, 37*4882a593Smuzhiyun enum amd_clockgating_state state); 38*4882a593Smuzhiyun void (*get_clockgating)(struct amdgpu_device *adev, u32 *flags); 39*4882a593Smuzhiyun void (*setup_vm_pt_regs)(struct amdgpu_device *adev, uint32_t vmid, 40*4882a593Smuzhiyun uint64_t page_table_base); 41*4882a593Smuzhiyun void (*update_power_gating)(struct amdgpu_device *adev, 42*4882a593Smuzhiyun bool enable); 43*4882a593Smuzhiyun void (*query_ras_error_status)(struct amdgpu_device *adev); 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct amdgpu_mmhub { 47*4882a593Smuzhiyun struct ras_common_if *ras_if; 48*4882a593Smuzhiyun const struct amdgpu_mmhub_funcs *funcs; 49*4882a593Smuzhiyun }; 50*4882a593Smuzhiyun 51*4882a593Smuzhiyun int amdgpu_mmhub_ras_late_init(struct amdgpu_device *adev); 52*4882a593Smuzhiyun void amdgpu_mmhub_ras_fini(struct amdgpu_device *adev); 53*4882a593Smuzhiyun #endif 54*4882a593Smuzhiyun 55