1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2019 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __AMDGPU_MES_H__ 25*4882a593Smuzhiyun #define __AMDGPU_MES_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #define AMDGPU_MES_MAX_COMPUTE_PIPES 8 28*4882a593Smuzhiyun #define AMDGPU_MES_MAX_GFX_PIPES 2 29*4882a593Smuzhiyun #define AMDGPU_MES_MAX_SDMA_PIPES 2 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun enum amdgpu_mes_priority_level { 32*4882a593Smuzhiyun AMDGPU_MES_PRIORITY_LEVEL_LOW = 0, 33*4882a593Smuzhiyun AMDGPU_MES_PRIORITY_LEVEL_NORMAL = 1, 34*4882a593Smuzhiyun AMDGPU_MES_PRIORITY_LEVEL_MEDIUM = 2, 35*4882a593Smuzhiyun AMDGPU_MES_PRIORITY_LEVEL_HIGH = 3, 36*4882a593Smuzhiyun AMDGPU_MES_PRIORITY_LEVEL_REALTIME = 4, 37*4882a593Smuzhiyun AMDGPU_MES_PRIORITY_NUM_LEVELS 38*4882a593Smuzhiyun }; 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun struct amdgpu_mes_funcs; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct amdgpu_mes { 43*4882a593Smuzhiyun struct amdgpu_device *adev; 44*4882a593Smuzhiyun 45*4882a593Smuzhiyun uint32_t total_max_queue; 46*4882a593Smuzhiyun uint32_t doorbell_id_offset; 47*4882a593Smuzhiyun uint32_t max_doorbell_slices; 48*4882a593Smuzhiyun 49*4882a593Smuzhiyun uint64_t default_process_quantum; 50*4882a593Smuzhiyun uint64_t default_gang_quantum; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun struct amdgpu_ring ring; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun const struct firmware *fw; 55*4882a593Smuzhiyun 56*4882a593Smuzhiyun /* mes ucode */ 57*4882a593Smuzhiyun struct amdgpu_bo *ucode_fw_obj; 58*4882a593Smuzhiyun uint64_t ucode_fw_gpu_addr; 59*4882a593Smuzhiyun uint32_t *ucode_fw_ptr; 60*4882a593Smuzhiyun uint32_t ucode_fw_version; 61*4882a593Smuzhiyun uint64_t uc_start_addr; 62*4882a593Smuzhiyun 63*4882a593Smuzhiyun /* mes ucode data */ 64*4882a593Smuzhiyun struct amdgpu_bo *data_fw_obj; 65*4882a593Smuzhiyun uint64_t data_fw_gpu_addr; 66*4882a593Smuzhiyun uint32_t *data_fw_ptr; 67*4882a593Smuzhiyun uint32_t data_fw_version; 68*4882a593Smuzhiyun uint64_t data_start_addr; 69*4882a593Smuzhiyun 70*4882a593Smuzhiyun /* eop gpu obj */ 71*4882a593Smuzhiyun struct amdgpu_bo *eop_gpu_obj; 72*4882a593Smuzhiyun uint64_t eop_gpu_addr; 73*4882a593Smuzhiyun 74*4882a593Smuzhiyun void *mqd_backup; 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun uint32_t vmid_mask_gfxhub; 77*4882a593Smuzhiyun uint32_t vmid_mask_mmhub; 78*4882a593Smuzhiyun uint32_t compute_hqd_mask[AMDGPU_MES_MAX_COMPUTE_PIPES]; 79*4882a593Smuzhiyun uint32_t gfx_hqd_mask[AMDGPU_MES_MAX_GFX_PIPES]; 80*4882a593Smuzhiyun uint32_t sdma_hqd_mask[AMDGPU_MES_MAX_SDMA_PIPES]; 81*4882a593Smuzhiyun uint32_t agreegated_doorbells[AMDGPU_MES_PRIORITY_NUM_LEVELS]; 82*4882a593Smuzhiyun uint32_t sch_ctx_offs; 83*4882a593Smuzhiyun uint64_t sch_ctx_gpu_addr; 84*4882a593Smuzhiyun uint64_t *sch_ctx_ptr; 85*4882a593Smuzhiyun uint32_t query_status_fence_offs; 86*4882a593Smuzhiyun uint64_t query_status_fence_gpu_addr; 87*4882a593Smuzhiyun uint64_t *query_status_fence_ptr; 88*4882a593Smuzhiyun 89*4882a593Smuzhiyun /* ip specific functions */ 90*4882a593Smuzhiyun const struct amdgpu_mes_funcs *funcs; 91*4882a593Smuzhiyun }; 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun struct mes_add_queue_input { 94*4882a593Smuzhiyun uint32_t process_id; 95*4882a593Smuzhiyun uint64_t page_table_base_addr; 96*4882a593Smuzhiyun uint64_t process_va_start; 97*4882a593Smuzhiyun uint64_t process_va_end; 98*4882a593Smuzhiyun uint64_t process_quantum; 99*4882a593Smuzhiyun uint64_t process_context_addr; 100*4882a593Smuzhiyun uint64_t gang_quantum; 101*4882a593Smuzhiyun uint64_t gang_context_addr; 102*4882a593Smuzhiyun uint32_t inprocess_gang_priority; 103*4882a593Smuzhiyun uint32_t gang_global_priority_level; 104*4882a593Smuzhiyun uint32_t doorbell_offset; 105*4882a593Smuzhiyun uint64_t mqd_addr; 106*4882a593Smuzhiyun uint64_t wptr_addr; 107*4882a593Smuzhiyun uint32_t queue_type; 108*4882a593Smuzhiyun uint32_t paging; 109*4882a593Smuzhiyun }; 110*4882a593Smuzhiyun 111*4882a593Smuzhiyun struct mes_remove_queue_input { 112*4882a593Smuzhiyun uint32_t doorbell_offset; 113*4882a593Smuzhiyun uint64_t gang_context_addr; 114*4882a593Smuzhiyun }; 115*4882a593Smuzhiyun 116*4882a593Smuzhiyun struct mes_suspend_gang_input { 117*4882a593Smuzhiyun bool suspend_all_gangs; 118*4882a593Smuzhiyun uint64_t gang_context_addr; 119*4882a593Smuzhiyun uint64_t suspend_fence_addr; 120*4882a593Smuzhiyun uint32_t suspend_fence_value; 121*4882a593Smuzhiyun }; 122*4882a593Smuzhiyun 123*4882a593Smuzhiyun struct mes_resume_gang_input { 124*4882a593Smuzhiyun bool resume_all_gangs; 125*4882a593Smuzhiyun uint64_t gang_context_addr; 126*4882a593Smuzhiyun }; 127*4882a593Smuzhiyun 128*4882a593Smuzhiyun struct amdgpu_mes_funcs { 129*4882a593Smuzhiyun int (*add_hw_queue)(struct amdgpu_mes *mes, 130*4882a593Smuzhiyun struct mes_add_queue_input *input); 131*4882a593Smuzhiyun 132*4882a593Smuzhiyun int (*remove_hw_queue)(struct amdgpu_mes *mes, 133*4882a593Smuzhiyun struct mes_remove_queue_input *input); 134*4882a593Smuzhiyun 135*4882a593Smuzhiyun int (*suspend_gang)(struct amdgpu_mes *mes, 136*4882a593Smuzhiyun struct mes_suspend_gang_input *input); 137*4882a593Smuzhiyun 138*4882a593Smuzhiyun int (*resume_gang)(struct amdgpu_mes *mes, 139*4882a593Smuzhiyun struct mes_resume_gang_input *input); 140*4882a593Smuzhiyun }; 141*4882a593Smuzhiyun 142*4882a593Smuzhiyun #endif /* __AMDGPU_MES_H__ */ 143