1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __AMDGPU_IRQ_H__ 25*4882a593Smuzhiyun #define __AMDGPU_IRQ_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #include <linux/irqdomain.h> 28*4882a593Smuzhiyun #include "soc15_ih_clientid.h" 29*4882a593Smuzhiyun #include "amdgpu_ih.h" 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #define AMDGPU_MAX_IRQ_SRC_ID 0x100 32*4882a593Smuzhiyun #define AMDGPU_MAX_IRQ_CLIENT_ID 0x100 33*4882a593Smuzhiyun 34*4882a593Smuzhiyun #define AMDGPU_IRQ_CLIENTID_LEGACY 0 35*4882a593Smuzhiyun #define AMDGPU_IRQ_CLIENTID_MAX SOC15_IH_CLIENTID_MAX 36*4882a593Smuzhiyun 37*4882a593Smuzhiyun #define AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW 4 38*4882a593Smuzhiyun 39*4882a593Smuzhiyun struct amdgpu_device; 40*4882a593Smuzhiyun 41*4882a593Smuzhiyun enum amdgpu_interrupt_state { 42*4882a593Smuzhiyun AMDGPU_IRQ_STATE_DISABLE, 43*4882a593Smuzhiyun AMDGPU_IRQ_STATE_ENABLE, 44*4882a593Smuzhiyun }; 45*4882a593Smuzhiyun 46*4882a593Smuzhiyun struct amdgpu_iv_entry { 47*4882a593Smuzhiyun unsigned client_id; 48*4882a593Smuzhiyun unsigned src_id; 49*4882a593Smuzhiyun unsigned ring_id; 50*4882a593Smuzhiyun unsigned vmid; 51*4882a593Smuzhiyun unsigned vmid_src; 52*4882a593Smuzhiyun uint64_t timestamp; 53*4882a593Smuzhiyun unsigned timestamp_src; 54*4882a593Smuzhiyun unsigned pasid; 55*4882a593Smuzhiyun unsigned pasid_src; 56*4882a593Smuzhiyun unsigned src_data[AMDGPU_IRQ_SRC_DATA_MAX_SIZE_DW]; 57*4882a593Smuzhiyun const uint32_t *iv_entry; 58*4882a593Smuzhiyun }; 59*4882a593Smuzhiyun 60*4882a593Smuzhiyun struct amdgpu_irq_src { 61*4882a593Smuzhiyun unsigned num_types; 62*4882a593Smuzhiyun atomic_t *enabled_types; 63*4882a593Smuzhiyun const struct amdgpu_irq_src_funcs *funcs; 64*4882a593Smuzhiyun void *data; 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun struct amdgpu_irq_client { 68*4882a593Smuzhiyun struct amdgpu_irq_src **sources; 69*4882a593Smuzhiyun }; 70*4882a593Smuzhiyun 71*4882a593Smuzhiyun /* provided by interrupt generating IP blocks */ 72*4882a593Smuzhiyun struct amdgpu_irq_src_funcs { 73*4882a593Smuzhiyun int (*set)(struct amdgpu_device *adev, struct amdgpu_irq_src *source, 74*4882a593Smuzhiyun unsigned type, enum amdgpu_interrupt_state state); 75*4882a593Smuzhiyun 76*4882a593Smuzhiyun int (*process)(struct amdgpu_device *adev, 77*4882a593Smuzhiyun struct amdgpu_irq_src *source, 78*4882a593Smuzhiyun struct amdgpu_iv_entry *entry); 79*4882a593Smuzhiyun }; 80*4882a593Smuzhiyun 81*4882a593Smuzhiyun struct amdgpu_irq { 82*4882a593Smuzhiyun bool installed; 83*4882a593Smuzhiyun spinlock_t lock; 84*4882a593Smuzhiyun /* interrupt sources */ 85*4882a593Smuzhiyun struct amdgpu_irq_client client[AMDGPU_IRQ_CLIENTID_MAX]; 86*4882a593Smuzhiyun 87*4882a593Smuzhiyun /* status, etc. */ 88*4882a593Smuzhiyun bool msi_enabled; /* msi enabled */ 89*4882a593Smuzhiyun 90*4882a593Smuzhiyun /* interrupt rings */ 91*4882a593Smuzhiyun struct amdgpu_ih_ring ih, ih1, ih2; 92*4882a593Smuzhiyun const struct amdgpu_ih_funcs *ih_funcs; 93*4882a593Smuzhiyun struct work_struct ih1_work, ih2_work; 94*4882a593Smuzhiyun struct amdgpu_irq_src self_irq; 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun /* gen irq stuff */ 97*4882a593Smuzhiyun struct irq_domain *domain; /* GPU irq controller domain */ 98*4882a593Smuzhiyun unsigned virq[AMDGPU_MAX_IRQ_SRC_ID]; 99*4882a593Smuzhiyun uint32_t srbm_soft_reset; 100*4882a593Smuzhiyun }; 101*4882a593Smuzhiyun 102*4882a593Smuzhiyun void amdgpu_irq_disable_all(struct amdgpu_device *adev); 103*4882a593Smuzhiyun irqreturn_t amdgpu_irq_handler(int irq, void *arg); 104*4882a593Smuzhiyun 105*4882a593Smuzhiyun int amdgpu_irq_init(struct amdgpu_device *adev); 106*4882a593Smuzhiyun void amdgpu_irq_fini(struct amdgpu_device *adev); 107*4882a593Smuzhiyun int amdgpu_irq_add_id(struct amdgpu_device *adev, 108*4882a593Smuzhiyun unsigned client_id, unsigned src_id, 109*4882a593Smuzhiyun struct amdgpu_irq_src *source); 110*4882a593Smuzhiyun void amdgpu_irq_dispatch(struct amdgpu_device *adev, 111*4882a593Smuzhiyun struct amdgpu_ih_ring *ih); 112*4882a593Smuzhiyun int amdgpu_irq_update(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 113*4882a593Smuzhiyun unsigned type); 114*4882a593Smuzhiyun int amdgpu_irq_get(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 115*4882a593Smuzhiyun unsigned type); 116*4882a593Smuzhiyun int amdgpu_irq_put(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 117*4882a593Smuzhiyun unsigned type); 118*4882a593Smuzhiyun bool amdgpu_irq_enabled(struct amdgpu_device *adev, struct amdgpu_irq_src *src, 119*4882a593Smuzhiyun unsigned type); 120*4882a593Smuzhiyun void amdgpu_irq_gpu_reset_resume_helper(struct amdgpu_device *adev); 121*4882a593Smuzhiyun 122*4882a593Smuzhiyun int amdgpu_irq_add_domain(struct amdgpu_device *adev); 123*4882a593Smuzhiyun void amdgpu_irq_remove_domain(struct amdgpu_device *adev); 124*4882a593Smuzhiyun unsigned amdgpu_irq_create_mapping(struct amdgpu_device *adev, unsigned src_id); 125*4882a593Smuzhiyun 126*4882a593Smuzhiyun #endif 127