1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2014 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __AMDGPU_IH_H__ 25*4882a593Smuzhiyun #define __AMDGPU_IH_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun /* Maximum number of IVs processed at once */ 28*4882a593Smuzhiyun #define AMDGPU_IH_MAX_NUM_IVS 32 29*4882a593Smuzhiyun 30*4882a593Smuzhiyun struct amdgpu_device; 31*4882a593Smuzhiyun struct amdgpu_iv_entry; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* 34*4882a593Smuzhiyun * R6xx+ IH ring 35*4882a593Smuzhiyun */ 36*4882a593Smuzhiyun struct amdgpu_ih_ring { 37*4882a593Smuzhiyun unsigned ring_size; 38*4882a593Smuzhiyun uint32_t ptr_mask; 39*4882a593Smuzhiyun u32 doorbell_index; 40*4882a593Smuzhiyun bool use_doorbell; 41*4882a593Smuzhiyun bool use_bus_addr; 42*4882a593Smuzhiyun 43*4882a593Smuzhiyun struct amdgpu_bo *ring_obj; 44*4882a593Smuzhiyun volatile uint32_t *ring; 45*4882a593Smuzhiyun uint64_t gpu_addr; 46*4882a593Smuzhiyun 47*4882a593Smuzhiyun uint64_t wptr_addr; 48*4882a593Smuzhiyun volatile uint32_t *wptr_cpu; 49*4882a593Smuzhiyun 50*4882a593Smuzhiyun uint64_t rptr_addr; 51*4882a593Smuzhiyun volatile uint32_t *rptr_cpu; 52*4882a593Smuzhiyun 53*4882a593Smuzhiyun bool enabled; 54*4882a593Smuzhiyun unsigned rptr; 55*4882a593Smuzhiyun atomic_t lock; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun /* provided by the ih block */ 59*4882a593Smuzhiyun struct amdgpu_ih_funcs { 60*4882a593Smuzhiyun /* ring read/write ptr handling, called from interrupt context */ 61*4882a593Smuzhiyun u32 (*get_wptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 62*4882a593Smuzhiyun void (*decode_iv)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 63*4882a593Smuzhiyun struct amdgpu_iv_entry *entry); 64*4882a593Smuzhiyun void (*set_rptr)(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 65*4882a593Smuzhiyun }; 66*4882a593Smuzhiyun 67*4882a593Smuzhiyun #define amdgpu_ih_get_wptr(adev, ih) (adev)->irq.ih_funcs->get_wptr((adev), (ih)) 68*4882a593Smuzhiyun #define amdgpu_ih_decode_iv(adev, iv) \ 69*4882a593Smuzhiyun (adev)->irq.ih_funcs->decode_iv((adev), (ih), (iv)) 70*4882a593Smuzhiyun #define amdgpu_ih_set_rptr(adev, ih) (adev)->irq.ih_funcs->set_rptr((adev), (ih)) 71*4882a593Smuzhiyun 72*4882a593Smuzhiyun int amdgpu_ih_ring_init(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih, 73*4882a593Smuzhiyun unsigned ring_size, bool use_bus_addr); 74*4882a593Smuzhiyun void amdgpu_ih_ring_fini(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 75*4882a593Smuzhiyun int amdgpu_ih_process(struct amdgpu_device *adev, struct amdgpu_ih_ring *ih); 76*4882a593Smuzhiyun 77*4882a593Smuzhiyun #endif 78