1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2017 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun #ifndef __AMDGPU_IDS_H__ 24*4882a593Smuzhiyun #define __AMDGPU_IDS_H__ 25*4882a593Smuzhiyun 26*4882a593Smuzhiyun #include <linux/types.h> 27*4882a593Smuzhiyun #include <linux/mutex.h> 28*4882a593Smuzhiyun #include <linux/list.h> 29*4882a593Smuzhiyun #include <linux/dma-fence.h> 30*4882a593Smuzhiyun 31*4882a593Smuzhiyun #include "amdgpu_sync.h" 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun /* maximum number of VMIDs */ 34*4882a593Smuzhiyun #define AMDGPU_NUM_VMID 16 35*4882a593Smuzhiyun 36*4882a593Smuzhiyun struct amdgpu_device; 37*4882a593Smuzhiyun struct amdgpu_vm; 38*4882a593Smuzhiyun struct amdgpu_ring; 39*4882a593Smuzhiyun struct amdgpu_sync; 40*4882a593Smuzhiyun struct amdgpu_job; 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct amdgpu_vmid { 43*4882a593Smuzhiyun struct list_head list; 44*4882a593Smuzhiyun struct amdgpu_sync active; 45*4882a593Smuzhiyun struct dma_fence *last_flush; 46*4882a593Smuzhiyun uint64_t owner; 47*4882a593Smuzhiyun 48*4882a593Smuzhiyun uint64_t pd_gpu_addr; 49*4882a593Smuzhiyun /* last flushed PD/PT update */ 50*4882a593Smuzhiyun struct dma_fence *flushed_updates; 51*4882a593Smuzhiyun 52*4882a593Smuzhiyun uint32_t current_gpu_reset_count; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun uint32_t gds_base; 55*4882a593Smuzhiyun uint32_t gds_size; 56*4882a593Smuzhiyun uint32_t gws_base; 57*4882a593Smuzhiyun uint32_t gws_size; 58*4882a593Smuzhiyun uint32_t oa_base; 59*4882a593Smuzhiyun uint32_t oa_size; 60*4882a593Smuzhiyun 61*4882a593Smuzhiyun unsigned pasid; 62*4882a593Smuzhiyun struct dma_fence *pasid_mapping; 63*4882a593Smuzhiyun }; 64*4882a593Smuzhiyun 65*4882a593Smuzhiyun struct amdgpu_vmid_mgr { 66*4882a593Smuzhiyun struct mutex lock; 67*4882a593Smuzhiyun unsigned num_ids; 68*4882a593Smuzhiyun struct list_head ids_lru; 69*4882a593Smuzhiyun struct amdgpu_vmid ids[AMDGPU_NUM_VMID]; 70*4882a593Smuzhiyun atomic_t reserved_vmid_num; 71*4882a593Smuzhiyun }; 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun int amdgpu_pasid_alloc(unsigned int bits); 74*4882a593Smuzhiyun void amdgpu_pasid_free(u32 pasid); 75*4882a593Smuzhiyun void amdgpu_pasid_free_delayed(struct dma_resv *resv, 76*4882a593Smuzhiyun u32 pasid); 77*4882a593Smuzhiyun 78*4882a593Smuzhiyun bool amdgpu_vmid_had_gpu_reset(struct amdgpu_device *adev, 79*4882a593Smuzhiyun struct amdgpu_vmid *id); 80*4882a593Smuzhiyun int amdgpu_vmid_alloc_reserved(struct amdgpu_device *adev, 81*4882a593Smuzhiyun struct amdgpu_vm *vm, 82*4882a593Smuzhiyun unsigned vmhub); 83*4882a593Smuzhiyun void amdgpu_vmid_free_reserved(struct amdgpu_device *adev, 84*4882a593Smuzhiyun struct amdgpu_vm *vm, 85*4882a593Smuzhiyun unsigned vmhub); 86*4882a593Smuzhiyun int amdgpu_vmid_grab(struct amdgpu_vm *vm, struct amdgpu_ring *ring, 87*4882a593Smuzhiyun struct amdgpu_sync *sync, struct dma_fence *fence, 88*4882a593Smuzhiyun struct amdgpu_job *job); 89*4882a593Smuzhiyun void amdgpu_vmid_reset(struct amdgpu_device *adev, unsigned vmhub, 90*4882a593Smuzhiyun unsigned vmid); 91*4882a593Smuzhiyun void amdgpu_vmid_reset_all(struct amdgpu_device *adev); 92*4882a593Smuzhiyun 93*4882a593Smuzhiyun void amdgpu_vmid_mgr_init(struct amdgpu_device *adev); 94*4882a593Smuzhiyun void amdgpu_vmid_mgr_fini(struct amdgpu_device *adev); 95*4882a593Smuzhiyun 96*4882a593Smuzhiyun #endif 97