1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2017 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __AMDGPU_GART_H__ 25*4882a593Smuzhiyun #define __AMDGPU_GART_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun #include <linux/types.h> 28*4882a593Smuzhiyun 29*4882a593Smuzhiyun /* 30*4882a593Smuzhiyun * GART structures, functions & helpers 31*4882a593Smuzhiyun */ 32*4882a593Smuzhiyun struct amdgpu_device; 33*4882a593Smuzhiyun struct amdgpu_bo; 34*4882a593Smuzhiyun 35*4882a593Smuzhiyun #define AMDGPU_GPU_PAGE_SIZE 4096 36*4882a593Smuzhiyun #define AMDGPU_GPU_PAGE_MASK (AMDGPU_GPU_PAGE_SIZE - 1) 37*4882a593Smuzhiyun #define AMDGPU_GPU_PAGE_SHIFT 12 38*4882a593Smuzhiyun #define AMDGPU_GPU_PAGE_ALIGN(a) (((a) + AMDGPU_GPU_PAGE_MASK) & ~AMDGPU_GPU_PAGE_MASK) 39*4882a593Smuzhiyun 40*4882a593Smuzhiyun #define AMDGPU_GPU_PAGES_IN_CPU_PAGE (PAGE_SIZE / AMDGPU_GPU_PAGE_SIZE) 41*4882a593Smuzhiyun 42*4882a593Smuzhiyun struct amdgpu_gart { 43*4882a593Smuzhiyun struct amdgpu_bo *bo; 44*4882a593Smuzhiyun /* CPU kmapped address of gart table */ 45*4882a593Smuzhiyun void *ptr; 46*4882a593Smuzhiyun unsigned num_gpu_pages; 47*4882a593Smuzhiyun unsigned num_cpu_pages; 48*4882a593Smuzhiyun unsigned table_size; 49*4882a593Smuzhiyun #ifdef CONFIG_DRM_AMDGPU_GART_DEBUGFS 50*4882a593Smuzhiyun struct page **pages; 51*4882a593Smuzhiyun #endif 52*4882a593Smuzhiyun bool ready; 53*4882a593Smuzhiyun 54*4882a593Smuzhiyun /* Asic default pte flags */ 55*4882a593Smuzhiyun uint64_t gart_pte_flags; 56*4882a593Smuzhiyun }; 57*4882a593Smuzhiyun 58*4882a593Smuzhiyun int amdgpu_gart_table_vram_alloc(struct amdgpu_device *adev); 59*4882a593Smuzhiyun void amdgpu_gart_table_vram_free(struct amdgpu_device *adev); 60*4882a593Smuzhiyun int amdgpu_gart_table_vram_pin(struct amdgpu_device *adev); 61*4882a593Smuzhiyun void amdgpu_gart_table_vram_unpin(struct amdgpu_device *adev); 62*4882a593Smuzhiyun int amdgpu_gart_init(struct amdgpu_device *adev); 63*4882a593Smuzhiyun void amdgpu_gart_fini(struct amdgpu_device *adev); 64*4882a593Smuzhiyun int amdgpu_gart_unbind(struct amdgpu_device *adev, uint64_t offset, 65*4882a593Smuzhiyun int pages); 66*4882a593Smuzhiyun int amdgpu_gart_map(struct amdgpu_device *adev, uint64_t offset, 67*4882a593Smuzhiyun int pages, dma_addr_t *dma_addr, uint64_t flags, 68*4882a593Smuzhiyun void *dst); 69*4882a593Smuzhiyun int amdgpu_gart_bind(struct amdgpu_device *adev, uint64_t offset, 70*4882a593Smuzhiyun int pages, struct page **pagelist, 71*4882a593Smuzhiyun dma_addr_t *dma_addr, uint64_t flags); 72*4882a593Smuzhiyun 73*4882a593Smuzhiyun #endif 74