1*4882a593Smuzhiyun /* 2*4882a593Smuzhiyun * Copyright 2020 Advanced Micro Devices, Inc. 3*4882a593Smuzhiyun * 4*4882a593Smuzhiyun * Permission is hereby granted, free of charge, to any person obtaining a 5*4882a593Smuzhiyun * copy of this software and associated documentation files (the "Software"), 6*4882a593Smuzhiyun * to deal in the Software without restriction, including without limitation 7*4882a593Smuzhiyun * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8*4882a593Smuzhiyun * and/or sell copies of the Software, and to permit persons to whom the 9*4882a593Smuzhiyun * Software is furnished to do so, subject to the following conditions: 10*4882a593Smuzhiyun * 11*4882a593Smuzhiyun * The above copyright notice and this permission notice shall be included in 12*4882a593Smuzhiyun * all copies or substantial portions of the Software. 13*4882a593Smuzhiyun * 14*4882a593Smuzhiyun * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15*4882a593Smuzhiyun * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16*4882a593Smuzhiyun * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17*4882a593Smuzhiyun * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18*4882a593Smuzhiyun * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19*4882a593Smuzhiyun * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20*4882a593Smuzhiyun * OTHER DEALINGS IN THE SOFTWARE. 21*4882a593Smuzhiyun * 22*4882a593Smuzhiyun */ 23*4882a593Smuzhiyun 24*4882a593Smuzhiyun #ifndef __AMDGPU_DF_H__ 25*4882a593Smuzhiyun #define __AMDGPU_DF_H__ 26*4882a593Smuzhiyun 27*4882a593Smuzhiyun struct amdgpu_df_hash_status { 28*4882a593Smuzhiyun bool hash_64k; 29*4882a593Smuzhiyun bool hash_2m; 30*4882a593Smuzhiyun bool hash_1g; 31*4882a593Smuzhiyun }; 32*4882a593Smuzhiyun 33*4882a593Smuzhiyun struct amdgpu_df_funcs { 34*4882a593Smuzhiyun void (*sw_init)(struct amdgpu_device *adev); 35*4882a593Smuzhiyun void (*sw_fini)(struct amdgpu_device *adev); 36*4882a593Smuzhiyun void (*enable_broadcast_mode)(struct amdgpu_device *adev, 37*4882a593Smuzhiyun bool enable); 38*4882a593Smuzhiyun u32 (*get_fb_channel_number)(struct amdgpu_device *adev); 39*4882a593Smuzhiyun u32 (*get_hbm_channel_number)(struct amdgpu_device *adev); 40*4882a593Smuzhiyun void (*update_medium_grain_clock_gating)(struct amdgpu_device *adev, 41*4882a593Smuzhiyun bool enable); 42*4882a593Smuzhiyun void (*get_clockgating_state)(struct amdgpu_device *adev, 43*4882a593Smuzhiyun u32 *flags); 44*4882a593Smuzhiyun void (*enable_ecc_force_par_wr_rmw)(struct amdgpu_device *adev, 45*4882a593Smuzhiyun bool enable); 46*4882a593Smuzhiyun int (*pmc_start)(struct amdgpu_device *adev, uint64_t config, 47*4882a593Smuzhiyun int is_add); 48*4882a593Smuzhiyun int (*pmc_stop)(struct amdgpu_device *adev, uint64_t config, 49*4882a593Smuzhiyun int is_remove); 50*4882a593Smuzhiyun void (*pmc_get_count)(struct amdgpu_device *adev, uint64_t config, 51*4882a593Smuzhiyun uint64_t *count); 52*4882a593Smuzhiyun uint64_t (*get_fica)(struct amdgpu_device *adev, uint32_t ficaa_val); 53*4882a593Smuzhiyun void (*set_fica)(struct amdgpu_device *adev, uint32_t ficaa_val, 54*4882a593Smuzhiyun uint32_t ficadl_val, uint32_t ficadh_val); 55*4882a593Smuzhiyun }; 56*4882a593Smuzhiyun 57*4882a593Smuzhiyun struct amdgpu_df { 58*4882a593Smuzhiyun struct amdgpu_df_hash_status hash_status; 59*4882a593Smuzhiyun const struct amdgpu_df_funcs *funcs; 60*4882a593Smuzhiyun }; 61*4882a593Smuzhiyun 62*4882a593Smuzhiyun #endif /* __AMDGPU_DF_H__ */ 63